Design Of General Digital Signal Processing Chip In MEMS Inertial Sensor

With the progress of the times,society is becoming more and more intelligent and digital,and the use rate of various MEMS(Micro-Electro-Mechanical System)sensors in contemporary society is also increasing,which makes the study of MEMS devices related knowledge Has a very significant meaning.At present,the domestic MEMS device interface circuit is still mainly focused on analog output.Relatively speaking,the relevant research and application of the digital output interface circuit is still lacking,so it is very meaningful to study the digital signal processing circuit of the MEMS inertial sensor.In this paper,a digital decimation filter and temperature compensation module are designed.The system can down-sample the Sigma Delta ADC output signal to Nyquist frequency accessories to implement SPI bus output and I2 C bus output.The digital decimation filter uses a three-stage filter structure.The first stage is a CIC filter,the second stage is a CIC compensation filter,and the third stage is a FIR lowpass filter.The extraction factor MCIC of the CIC filter is variable,MCIC=32?64?···?2048.The digital decimation filter module adjusts the change of the decimation factor of the whole system by adjusting the size of MCIC,so as to realize the control of the overall passband cutoff frequency,stopband cutoff frequency and output signal frequency,and achieve a certain universality.The function of the second-stage CIC compensation filter is to perform passband compensation on the CIC filter to flatten its passband,and its extraction factor MCOM=2.The function of the third-stage FIR low-pass filter is to further downsample and filter out highfrequency noise,and its extraction factor MFIR=2.Each stage filter uses a variety of optimizations,which can effectively improve the filter efficiency.The CIC filter adopts the "five-level integration-decimation-fivelevel differentiation" structure.The CIC compensation filter and FIR low-pass filter use CSD coding and two-phase decomposition to make the filter module run faster,the area becomes smaller,and the power consumption becomes lower.The designed temperature compensation module can write the temperature compensation coefficient into the register according to the specific situation,and call the coefficient to realize the third-order polynomial temperature compensation.When input signal frequency f=31.25 Hz,sampling frequency fs=2048k Hz,signal-to-noise ratio SNR=129.9dB,in system level verification,MCIC=32,overall extraction factor is M=128,and filter SNR=130.7dB,130.5dB,130.5dB;when using verilog language RTL behavior level implementation for digital decimation filter,conduct behavior level verification to obtain MCIR=32,FIR filter output signal SNR=130.82 dB when MIC=128.