The Design Of Digital Compensation Filter In TMR Magnetometer

With the rapid development of technology,businesses demand for data acquisition and processing are becoming increasingly large.ADC and DAC as an interface between analog and digital,have become an indispensable part of the data acquisition system.In recent years,Sigma-Delta ADC with high speed,high precision,high linearity,low power consumption,easy integration,and other advantages,is gradually replacing traditional ADCs in communication and digital signal processing.The Sigma-Delta ADC consists of a modulator and a digital decimation filter that decides the power and area of the Sigma-Delta ADC.Reducing the power consumption and area of the digital decimation filter is important for improving the performance of the data acquisition and processing system.In this paper,the digital decimation filter in Sigma-Delta ADC is optimized for geomagnetic field measurement and is used in the signal acquisition system of TMR(Tunnel Magneto Resistance)sensor.The overall filter uses a three-stage decimation structure: CIC filter(MCIC is variable),CIC compensation filter(MCOMP=2),FIR low-pass filter(MFIRLP=2).And the behavioral model and behavioral simulation are established based on MATLAB.When the sampling frequency fs = 2048 kHz,the signal frequency f = 31.25 Hz,the input signal noise floor is-150 dB,the SNR drop of the filter model's output signal is within 0.3dB.The three filter stages in the decimation filter are optimized.The first-stage CIC filter adopts the "5-stage integrator—decimator—5-stage differentiator" structure,the internal adder and the register at each stage are designed as 61 bits,and the decimation factor MCIC = 32,64,128,256,512,1024,2048,4096.The second and third stage filters adopt the two-phase filter structure with firstly decimating and then filtering,each phase filter adopts symmetrical structure,and the filter coefficients are coded by CSD.In addition,the two filter stages have stopband attenuation of 90 dB and 53 dB,respectively.These optimizations effectively reduce the power and area of the chip.After coding with Verilog HDL,the overall passband ripple of the filter is less than 0.005 dB and the maximum output sampling frequency is 16 kHz.The corresponding bandwidth and flat passband width are 5872 Hz and 5kHz,respectively(fs = 2048kHz).Under the same conditions as the behavioral simulation,the SNR drop of the RTL simulation output signal is within 0.3dB.Under the condition of 0.35?m 5V standard CMOS process and 10 MHz clock frequency constraint,the area of the filter layout is 3.27?3.4mm2.The digital decimation filter is used to construct the TMR sensor data acquisition and processing hardware platform,and then the TMR sensor uses the hardware platform and software programming to compensate the error digitally.The compensation result shows that the non-linearity of the TMR sensor is improved from 0.27% to 0.1% and the amount of offset compensation is 58741 nT.