Research And Design Of Digital Decimation Filter

The paper is based on one multimedia SoC project, which will be called as"nightingale"in the following chapters. Synchronous Serial Interface and I2C modules are the important modules of the SoC chip. Digital decimation filter is the digital part of Sigma-Delta modulater. Unlike traditional analog-digital modulators, Sigma-Delta modulator can reduce sampling frequency.Different structures of digital decimation filters are provided in this thesis, and the implementation methods of"Synchronous Serial interface","I2C"are also described.In this paper, the creative points are listed as following:Firstly, accordidng to the detailed application of external chip,provide overall architecture which is able to support multi audio path to meet the bottle neck .Based on the research, the author also analyze chip external CODEC's application methods, Supply three application cases,analyze the timing waveform and performance in detail. Secondly, aimed the limited sampling frequency of traditional analog/digital converters, propose digital decimation filter's structure. In order to improve the performance of digital decimation filter, use comb filters as front-end filters ,use other FIR digital filters as the backend filters。Base on the detailed research and design of decimation filters,the final design owns the best performance,realize sigma-delta modulaters'digital part.Totally, during the process of project design, the author utilize advanced EDA tools (for example VCS, DEBUSSY, MATLAB, MODELSIM and so on ),advanced SoC chip design technology . The paper also do further research and analysis about interface protocol and how to realize the hardware architecture. The whole project not only covered the softerware design and hardware design, but also coverd system design to RTL coding ,which make good preparation for the hardware realization fo CODEC.The multimedia SoC chip had been taped out successfully in TSMC using 180 narometer process. According to the test result based on the sample chip, the SSI and I2C modules which the author is responsible for are able to function normally.