Frequency Implement Decimation Factor Variable Digital Down

DDC is a technology to intermediate frequency digital signal to the zero intermediate frequency down-conversion and signal rate dropped to a technology suitable for general-purpose digital signal processing devices processing rate. And the market in DDC extracting high multiples、stable performance, but its flexibility is poor, doesn’t bring the advantages of soft radio is well represented. FPGA rapid development in recent years, the powerful processing capability、short development cycle and can now line refactoring make it play an increasingly important role in the research and development of software radio.Microwave test system receiving the signals of different frequencies, such as0.8MHz、30MHz,50MHz. These received signals need design multiple digital down converter resources will greatly occupied. To solve this problem, we have a depth research and make a factor variable down conversion realization. In this design, each decimation factor digital down conversion is timesharing. To ensure the correctness and practicality of the whole system. This paper studies analyze the main modules of DDC:NCO module, CIC filter module, the HB filter module and FIR filter module and achieve the main algorithm analysis to every module. Using matlab for the allocation of the different decimation factor of each filter decimation multiples. And determine the various parameters of the filter such as the order of filter. the IP CORE of the NCO、the CIC filter、 HB filter and FIR filter are called, and the parameters are selected. The digital down conversion system using verilog language to build, in real-time signal observed in signaltap and oscilloscope and spectrum analysis in matlab for multiple decimation factors. The results show that, for different decimation factor of each module and the system as a whole functions to meet the design requirements, and verify that the correctness of the design.