Research And Design Of High-Performance Digital Decimation Filter For Precision ?-? ADC

In the fields of weak signal processing such as modern electronic measurement systems,biomedical instruments,and sonar signal detection,there is an urgent need for high-precision(resolution>16 bits)ADCs.The?-?ADC can adopt over-sampling technology,noise shaping technology and high-precision digital signal processing technology,which can improve performance effectively and obtain higher resolution.The digital decimation filter is an important part of the?-?ADC,its main function is to decimate and filter the output of the?-?ADC front-end modulator,and restore the original information of the sampled signal.The area and power consumption of the decimation filter account for a relatively large portion of the entire?-?ADC.This thesis mainly studies the architecture of the digital decimation filter in a high-precision?-?ADC with a resolution of up to 24 bits,and optimizes the area and power consumption of the filter while ensuring the noise of the system as low as possible.Based on the study of the different architectures of the digital decimation filter,this design puts forward a four-stage cascaded digital decimation filter structure which is made up of a CIC filter,an improved compensation filter and two-stage HB filters.An ISOP filter that has better passband compensation effect,which is adopted in the system to obtain better passband compensation effect and less hardware overhead.Besides,the system adopts the cosine filter with better stopband attenuation effect,so the stop-band attenuation is increased greatly.Meanwhile reduce the influence of in-band aliasing effectively on the in-band signal.A non-recursive structure of the CIC filter and a cosine filter are combined to reduce the hardware overhead in the circuit design.A new scheme is proposed to improve the performance of the traditional CIC cascaded cosine filter.It adopts a larger multiple downsampling rate in the front stages and a non-recursive structure with a low multiple downsampling rate in the latter stages,and hardware sharing and pipeline technology are adopted,which deeply decreases the area and power consumption of the circuit,enhances the velocity of the system and decreases the output delay of samples.Moreover,according to the characteristics that the HB filter coefficients are symmetrical and nearly half of the coefficients are zero,and CSD encoding filter coefficients uses less computational complexity,pipeline technology is also applied to the design of the latter two HB filters,which further reduces the area and power consumption of the system.In the design,the digital decimation filter was verified by system-level simulation and hardware-level digital-analog hybrid simulation.The SNDR of the hardware-level?-?ADC is 143.8 d B and the ENOB of the hardware-level?-?ADC is 23.59 bits.The quantization error introduced by the filter is 2.1 d B,and the delay time of the filter is 57860 clocks,which meets the design specifications.Finally,logic synthesis,static timing analysis and layout synthesis are studied for the design on the account of the TSMC 0.18 um CMOS process.The results show that the digital decimation filter layout area is 0.893 mm~2,the power consumption is 0.178 m W.