Development Of Wideband Multichannel Signal Generator Based On FPGA

With the development of modern technology,radar has become more and more powerful,which plays a vital role in the field of national defense and civil life.The complexity of modern radar functions requires a significant increase in performance based on the frequency,bandwidth,modulation type,and agility speed of the signal,meanwhile,the types of signal waveforms tend to be arbitrary.High-performance arbitrary signal generators can not only produce low-noise,low-jitter and pre-emphasized broadband multi-channel RF signals,but also reproduce distortion-free real signals,which is extremely important in the development and testing process of modern radar systems.The system architecture of the wideband multi-channel signal generator is analyzed in the thesis,determines the design architecture of the host computer combined with FPGA and high-speed DAC.Because of the high flexibility of the upper computer development,arbitrary waveform baseband signals can be generated by mathematical modeling tools.Then FPGA is use to realize the high-speed digital up-conversion processing of the baseband signal.Finally,the optional second-level digital up-conversion processing and digital-to-analog conversion is performed by the high-speed DAC to achieve the output of the expected analog signal.The principle of wideband multi-channel signal generator is introduced in the thesis,including the direct digital signal synthesis technology and the principle of digital up-conversion.According to the requirements for signals of modern radar,the implementation plan of the system is designed.Then,the process of realization of wideband multi-channel signal generator based on FPGA is described.The design of ping-pong storage structure based on DDR3 is described in detail,to buffer the baseband signal from the upper computer.This part focuses on the implementation structure of the first-stage high-speed digital up conversion,including the design of anti-aliasing filters and parallel numerically controlled oscillators.The sampling rate of baseband signal is increased to GHz while the signal spectrum is shifted to the intermediate frequency.After that,the high-speed communication based on JESD204 B agreement between FPGA and high-speed DAC as well as the overall design flow of high-speed DAC are introduced,to obtain expected analog signal.Finally,the third-generation high-performance PCI Express 3.0 serial bus technology is focused on,including PCI-e bus related specifications,PCI-e hard core design in FPGA,and DMA controller design for high-speed communications,which realize high-speed data transmission between host computer and FPGA.