Design Of Digital Post-Processing Circuit Of Band-Pass Sigma-Delta ADC

With the rapid development of design technology of integrated circuit and semiconductor technology, the analog-to-digital converters are advancing towards high speed, high resolution and low power. Its high accuracy, wide tolerance of the process requirements make ?-? ADC concerned in the field of high-precision signal processing. High performance band-pass ?-? ADC is the key block of the digital IF receiver, it can be used to digitize the narrowband intermediate frequency signals effectively. It is suitable for the performance and integration of the receivers systems with the multi-mode potential. Therefore, the main purpose of this dissertation is to design a digital down converter, which is the key part of band-pass ?-? ADC.With basic principle and structure of ?-? ADC, this thesis presents significant research on the design theory and methods of digital down converter. According to the DDC's overall performance, the design requirements of different blocks are discussed. In the case of considering the performance and power consumption, the design parameters and the circuit implementation structure of each module are optimized. NCO employ the combination of the lookup table and the Taylor expansion to obtain the values of sine and cosine function, which takes into account the speed, accuracy, resources and other aspects of the requirements. Furthermore, the lookup table can be replaced by decoder to save hardware resources. The CIC filter adopts classic recursive structure, which is beneficial to code and layout implementation with no multipliers. Fir compensation filter uses two phase transposition symmetry structure whose filtering operations is after down sampling, which can reduce the work frequency and improves the calculation efficiency. According to the characteristics of the half band filter, a realization structure of half band filter based on the weak correlation between the frequency response of the filter and the quantization of the coefficients is put forward, which can reduce the number of coefficient quantization under the premise of ensuring the filtering performance. Meanwhile, Canonic Signed Digit (CSD) number is used in coding the filter coefficient to decrease the computation and complexity.The proposed techniques are applied to the design of a digital down converter of 13-bit band-pass ?-? ADC using 0.18?m CMOS technology, with input sampling frequency of 26 MHz and output sampling frequency of 812.5 kHz. Test results show that with a down sampling ratio of 32 times, intermediate frequency of 500 kHz and a SNDR of 65.3dB are achieve. The entire filter consumes a power of 4mW at 1.8 V supply with an area of 1000×600?m~2.