| With the development of integrated circuits,the number of cores integrated on a single chip is increasing,and the processor has entered the era of many cores.Compared with the traditional bus interconnection,high-bandwidth and good scability on-chip networks are more and more widly used.As an important indicator to measure the performance of the on-chip network,the problem of network delay becomes more and more unavoidable as the scale of the on-chip network expands.At the same time,for some non-global access applications,there is a problem of global uniform access structure redundancy in the conventional mesh structure on-chip network.In order to reduce the network delay and simplify the router structure,it is very important to study and optimize the on-chip network structue.First,the working principle of the conventional mesh NoC router is analyzed,and the influence of the parameters such as the number of virtual channels,the depth of the input buffer and the average length of the data packet on the network delay is studied using the conventional structure.On this basis,for the application scenario of small injection rate that this research focuses on,a double-ring on-chip network structure with single virtual channel data bypass is proposed.The double-ring on-chip network divides the network into several separate ring networks in the form of horizontal rings and vertical rings,and the data transmission between the rings does not interfere each other.At the same time,a bypass structure is added to the router so that data packets can be transmitted to multiple nodes in a single cycle.Only one virtual channel is set on the input port of the router to reduce the area and power consumption caused by multiple virtual channels.The universal router interface is adopted to ensure that the router is compatible with the conventional topology.Then the Noxim simulator is used to model the proposed double-ring on-chip network,and the average network delay is analyzed under multiple parameter configurations,and compared with the mesh network.The results show that under low load condition,for an 8x8 network scale,the network delay of a double-ring NoC that can bypass 4 nodes in a single cycle is 51%lower than the mesh on-chip network with the same parameter configuration.Then the System Verilog language is used to perform the implementation of the double-ring NoC.And the VCS is used to perform the functional simulation on the system and each submodule.The result shows that the data packet can be transmitted to multiple nodes in a single clock cycle to achieve the desired goal.Finally,the MIFS40nm process is used to logically sysnthesize the double-ring NoC.The result shows that the area of a single router is 4832.973μm2,and the system frequency can reach 763MHz when a data can bypass two nodes in one cycle. |
