Research On The Architecture Key Techniques Of Application-Specific Multi-core Processor

With the rapid development of multimedia service and wireless communication technology, the demand for multimedia applications and high-speed, reliable and seamless wireless communications applications continues to expand. Thus for the specific application of multimedia broadcasting and wireless communication technology, the demand for the multi-core processor becomes particularly important. The rise and development of the multi-core processor, largely due to the continuous improvement of integrated circuit manufacturing technology and increasingly sophisticated architectural design. The core of multimedia broadcasting and wireless communication technology information processing is a processor. This paper focuses on the actual need of future-oriented multimedia broadcasting and wireless communication algorithms, studying on the new processor architecture technology, combining the characteristics of processor architectures and the demand of specific applications to provide new solutions to the future development.As for the application requirements of multimedia broadcasting, wireless communication and channel coding technique, this paper presents a multi-core processor architecture orienting the specific application. The main work is as follows :1.The multi-core processor integrates 15 processor computing unit and a shared memory node cells on a single chip which is based on 2D-Mesh network. And it achieves a communication mechanism between cores of the shared storage.2.Based on the MIPS instruction, a single-core processor compatible with the MIPS instruction set is achieved. Based on ISE14.6, the processor has got its maximum operating frequency of 91.533 MHz and its minimum period of 10.925 ns, which operates on Kintex ?-7 family XC7K70T-2fbg676 hardware platform. In order to achieve the low-overhead and low-latency characteristic, the algorithm has been implemented and optimized.3.Based on the advancing routing technologies and forecasting techniques, this paper presents a low-overhead and low-latency pipelined wormhole virtual channel router,which speculate only two cycles. The router is added the input port of the request mask shielding modules and shields the two cases.To prevent the packet loss and enhance utilization rate of the data cache(buffer) resource,this paper proposed a credit-based flow control mechanism. Based on the results of ISE14.6, its comprehensive maximum operating frequency is 297.983 MHz, the minimum period is 3.356 ns. To verify the low-overhead and low-latency characteristic of the router, this paper designed and implemented several other conventional router architecture. By comparison, the router’s advantage of delay and overhead has been drawn. Finally, this paper simulates real application to get their average latency by Splash-2 applications.4.Based on the single-core MIPS processor and low overhead and low latency router,a low-cost and low-latency network interface based on a Wishbone bus is achieved.In order to enhance its low-cost and low-latency performance, reconfigurable units asynchronous FIFO are designed and optimized. And the reconfigurable herein FIFO area and power overhead structure are drawn by DC synthesis integrated tool.The overhead, frequency and latency performance of the two network interfaces are synthesized by ISE14.6.5.In order to realize the completeness of the paper, it has referred to other members of the research team,working on multi-core processors in LDPC decoder, H.264 video decoder and FFT decoder and other aspects of the mapping method.