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Study Of Network Assignment And Service Quality For NoC

Posted on:2013-02-16Degree:DoctorType:Dissertation
Country:ChinaCandidate:L QuanFull Text:PDF
GTID:1118330371470478Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
NoC(Network-on-Chip), due to its advantages such as good scalability, transmission parallelism and flexibility, is considered as an emerging on-chip communication architecture suitable for large-scale on-chip multiprocessing system instead of the traditional on-chip interconnection schemes.Network assignment is an important step in the NoC design flow. As single dimension-ordered routing used in path allocation limits the solution space of mapping problem for networks on chip, a network assignment approach based on dual dimension-ordered routing was proposed. Dual dimension-ordered routing method was adopted in the path allocation step, and a genetic algorithm was developed to minimize dynamic and static energy consumption subject to bandwidth, delay and lock-free constraints. Experimental results showed that the proposed algorithm was able to enlarge solution space, reduce link bandwidth requirements by 6.3% in average, and find less energy consumption solutions at any bandwidth circumstance.On-chip network applications has high quality of communication requirements. To meet the low latency and low jitter transmission requirements of real-time applications in MPSoC (Multi-Processing Systems-on-Chip), an efficient QoS scheme for NoC was proposed. The scheme first classified transmission messages into three types, which were in high-to-low priority order:latency critical (control signal, etc.), jitter critical (usually burst data) and non-critical. Then the scheme utilized advanced applying and dynamic scheduling mechanism to appropriately made use of bypass channels in routers. It allocated resources and handled conflicts sensibly according to communication tasks' requirements and priorities. Concretely, the mechanism for low latency transmission service used specific virtual channels, flexible bypass, on/off flow control and blocked-packet's priority upgrading to forward latency critical messages as soon as possible, while for low jitter transmission service it employed virtual channel reservation, adaptive routing algorithm, and reserved-channel no-load bypass to maintain successive transmission and low latency variation of jitter critical messages. The control logic's VLSI design of the QoS scheme was also presented, including virtual channel pre-arbitration module, bypass arbitration module, and switch allocator. Experiment results showed that average delay of latency-critical messages is reduced by 41%, and average latency difference of burst data is reduced by 39% compared to conventional method which only based on priority and specific virtual channel. Thus the proposed scheme can provide high-quality differentiated service for SoC applications.Transmit data to the destination reliably and correctly is another basic on-chip network quality of service requirements. As semiconductor device dimensions'shrinking and SoC system voltage dropping, factors like crosstalk noise significantly affecting the reliability of the transmission link, NoC should use some error control scheme to maintain the correctness and reliability of data transfer. Integrated considered data transfer capacity, time constraints, voltage swing's effect for reliability, this article take single link's performablity model as foundation, by analyzing different error control schemes'principle and features, established performablity model for communication path, and evaluated switch to switch error correction, switch to switch retransmit, end to end retransmit, and mixed error control mechanism schemes protection effect. Using the model, this article also proposed a reliability optimization method under energy consumption constrain. Experimental section using simple application case showed the usage of the performablity model established in this article, consists of comparing the different error control scheme's performablity, and searching voltage configurations to maximize the performablity under certain energy consumption constraints. Experimental results showed that, under loose time constraint conditions, communications path under mixed scheme has a lower probability of error; under tight time constraint conditions, switch to switch retransmission scheme has a better protection for data transfer.
Keywords/Search Tags:Network-on-Chip, Network assignment, Dual dimension-ordered routing, Genetic algorithm, Multi-constrain optimization, Quality-of-Service, Bypass channel, Low latency service, Low jitter service, Reliability analysis, Performability
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