Study Of Power Optimization And Multicast Routing Based On SMART In NoC

With the rapid development of integrated circuit and motivation for the high performance computing,the development of System-on-Chip(SoC)follows the trends as below:from multi-core to many-core,from bus to network,from centralized storage to distributed memory.Network-on-Chip becomes a promising interconnection architecture for many-core system due to high bandwidth,low power consumption and good scalability.The basic processing unit for large-scale parallel computing is changed from a processor to a core,and the parallelism of program is effected greatly by the communication capability among the cores.Multicast is a typical communication mode which is ubiquitous in large-scale parallel computing,and is a key factor that affects the parallel performance of chip multiprocessor(CMP).An efficient architecture of multicast router becomes an important research topic in on-chip communication.Network-on-Chip(NoC)consume an increasing fraction of the chip power,reducing it is increasingly important for energy proportional computing.Based on SMART,this dissertation studies power optimization and multicast for No C.The main contributions of this thesis are as follows.This paper studied an on-chip network called SMART(Single-cycle Multi-hop Asynchronous Repeated Traversal).It present a single-cycle data-path all the way from the source to the destination.We analyze its features and evaluate its performance.Router parking No C is proposed based on SMART.In this design,router Maintain network connectivity after it is powered off and reduce the increase in interconnect latency due to power saving.Multicast routing algorithm is proposed based on SMART.Which can accomplish a broadcast within a single-cycle per-dimension.