Research Of Low Latency And Low Power For Noc Based On Multi-core

With the advance in production process, the semiconductor technology developsquickly, which makes the degree of integration of transistors and other components onthe processor becomes higher and higher, so the on-chip multi-processor architectureemerged. However, with the increasing numbers of kernels and other components, themethod of communication on-chip, improving the quality of communication and theutilization of resources become the main research directions and hotspots. In order tosolve these problems, the NoC(network-on-chip) emerged, it means connecting theresources on the chip by routers, including components such as kernel, cache andcontrollers, making each component requests or replies by routers. Traditional buscommunication communicates through bus, when it has larger scale communication,which will cause communication block, especially in the multi-processor structure,this scenario is much more serious. So the quality of communication is dramaticallyincreased by NoC, which controls the communication by routers.NoC brought the revolutionary change for on-chip communication, but it facedmany problems to be solved, because of the addition of routers and other componentssuch as switching circuit and storage unit, which makes the limited on-chip areabecomes more compact, even more, we need to expand the on-chip area to achieveour requirements. As the routers are used to forward data, in the process of datageneration and routing, the steps needed for data communication are used such aspackaging, buffering and arbitration, these will increase the communication latency tosome extent. The routers and other components including some buffers and logicstructure are added, using these components use electricity, it is conceivable that thiswill have influence on the power consumption of system, and the proportion of thepower consumption of buffers is big, this in inconsistent with the current requirementof lower power consumption. Currently some research has proposed improved waysand principles, including the improved topology, transformation of communication,however, few people have considered the improvement of transfer strategy of internaldata in the router, or the advance in data storage and data exchange inside the router,and the fairness and distribution strategy of data after routing were not analyzed.To curve the above problems, this article combines the improvement of topologyand routing strategy, proposed a way of data communication based on fairness andefficiency. Some advices of improvement based on fairness were suggested, as thereare more and more components, the communication distance would be longer, so thecommunication links were added in the topology, which made the averagecommunication distance shorter. In the strategy of arbitration institution inside therouter polling the buffers, the consideration based on fairness were introduced，so the probability of data through the exchange area stayed in the relative balance area. Thisproject decreased the network latency by shortening the communication distance,making data have chances to go through the router, unlikely caused local data blockbecause of waiting too long time. Based on the above, the routing strategy based onefficiency were proposed, connecting multiple kernels to the same router, adjustingthe storage strategy of data buffer inside the router, making full use of data buffer, thisshortened the communication latency, plus the improvement of topology, decreasedthe power consumption.The proposed two schemes aimed at improving the communication qualityon-chip and communication efficiency, decreasing network latency and powerconsumption. The two schemes were in hierarchical relationships, from one based onfairness to the other based on efficiency, it improved communication quality on-chipsignificantly, meanwhile leaving the space for further work. Our experiment used aGem5as a full system simulation platform and the PARSEC benchmark as our testprogram, simulated the basic topology and simple routing strategy, the strategy addinglinks and fairness and the strategy of sharing routers and efficient use of buffers, andthe three strategies were verified and compared using the topology with16cores or64cores, including the horizontal comparison and the vertical comparison. The resultshowed that compared with the scheme having no any improvements, the proposedtwo schemes improved the performance and decreased power consumptionsignificantly, the second scheme decreased the communication latency by18%through adding communication links and improving the fairness, the third schemedecreased the communication latency by30%and the18%reduction in powerconsumption through adding the utilization of data buffer and decreasing the numberof routers. Compared with the topology with16cores, the topology with64coresimproved performance significantly. So the proposed scheme is suitable for thecurrent network-on-chip structure of multi-core, it has a very good room fordevelopment.