Efficient Network On Chip Architecture: Router Inside The Core

In recent years, improvement of manufacture has made Chip Multi-Processor (CMP) the primary way for processor performance improvement. With the growing number of core and frequent communication on chip, researchers have paid more and more attention to Network on Chip (NOC). At present most of researches about NOC focused on the various optimizations of router components, which assumes that router is outside the core and failed to make use of local resource of core such as memory and bandwidth.By researching into internal storage of router, this paper integrates router into corresponding core of which based on characteristics such as local memory and resourceful bandwidth. This can lead to an efficient and power-saving router by buffer elimination, buffer improvement and packet transmission optimization.This paper first compares Network on Chip with Macro Network, classifies internal storage of router, and raised an efficient NOC architecture: Router inside the core. Then, four optimizations (Send buffer Optimization, Exit Buffer Optimization, Sending Head Flit Ahead, Tail Flit elimination) are proposed based on analysis of router's internal buffer utilization and packet transmission process to reduce average packet latency and power of network..Simulation experiments show that Send Buffer Optimization and Send Head Flit Ahead optimization can effectively reduce average latency by 24.3% and power by 9% when buffer has larger depth. By mixing Exit Buffer Optimize and Tail Flit Elimination, it will eventually reduce average latency by 30.5% and of power by 37.8% though buffer is of small size. Besides, according to calculation, integrating router into core can save 9.3% chip area.To sum up, Router-Inside-the-Core architecture and four optimizations proposed in this paper are efficient and feasible. It can save chip area, reduce average latency and power consumption effectively.