Research Of Fast Locking Fractional-N All Digital Phase Locked Loop

It is necessary to provide a stable local clock frequency synthesizer in the image sensor chip,which can provide low-noise clocks with different frequencies for the internal digital circuit.The frequency synthesizer commonly used is the CPPLL.ADPLL is a better choice under more advanced CMOS processes because it offers smaller area,programmability,extensive self-calibration capabilities,and ease of migration.However,the TDC in traditional ADPLL is a block with high power consumption.In this paper,a kind of snapshot TDC assisted by DTC is used to replace the traditional TDC.This TDC reduces the operating frequency from the traditional GHz level to the MHz level,so as to realize lower power consumption and simplify the design difficulty of TDC.In order to realize fractional frequency division,sigma-delta fractional frequency divider is used in both CPPLL and traditional ADPLL,but it has the problem of severefractional spurs.In this paper,the DTCis used to realize fractional frequency division,which can avoid introducing large fractional spurs.The locking speed of CPPLL is limited by the charge pump current and loop parameters,so it is difficult to increase significantly.In ADPLL,the fast locking algorithm can be introduced to predict the control words in advance to realize the fast locking.This paper aims to solve the power consumption problem of traditional ADPLL architecture,further reduce the power consumption and noise,and improve the locking speed.Based on the analysis of the design requirements and the existing architecture,anADPLL with low power consumption and low noise is proposed for the application of image sensors.A high linearity digitalcontrolledring oscillator provides a high frequency clock.The fast locking algorithm based on frequency prediction algorithm improves the locking speed of ADPLL.This ADPLL provides a better choice for on-chip clock applications for image sensors than the analog CPPLL.Designed in 180 nm 1P4MCMOS process,the ADPLL works at a power supply voltage of 1.8V.When outputting1.5GHz frequency,the overall power consumption of the system is 4.56 mW,and the measured rms jitter is 1.71ps(integrated from 1kHz to 100MHz).