A Fast Locking Digital PLL Design

Digital phased locked loop is an important synchronization circuit in the communication system.It can make the output signal in frequency and phase synchronization with the input signal,so it is widely used in areas such as computers and communications.Digital phased locked loop plays an important role in the digital synchronization system,and a fast locking DPLL is designed according to the requirement of its application.This thesis chooses the appropriate circuit structure and uses the circuit structure of phase detection module combining with charge pump which contains a combination of coarse and fine current source to achieve fast locking.The two current sources automatically control the bandwidth of the DPLL.When DPLL is out of lock, the bandwidth is increased to achieve fast locking, and it is reduced for stability when DPLL is in the state of locking.This thesis focuses on the research of the circuit structure of phase detector module combining with charge pump which contains a combination of coarse and fine current source.When designing the charge pump,this thesis primarily considers the non-ideal effects such as the match of the switches,the channel charge injection effect and the current mismatch.Finally,this paper presents simulation results of each module of the DPLL, as well as the entire system.The design was implemented with0.35um CMOS process with a3.3V power supply.In the variation of temperature(-30℃-60℃),the input frequency range is75MHz-200MHz,the output frequency range is75MHz-200MHz and the duty cycle of output signal is52.6%-62.5%. The design used Cadence’s Spectre for circuit simulation under various PVT conditions. The simulation result shows that the designed DPLL can work under various PVT conditions, and the power consumption is less than4mW, the locking time was less2us and its reduction in the range of51.5%-66.6%was achieved compared with the circuit structure which has no coarse-tuning current source. When the input frequency hop occur, the locking time is0.562us, and its reduction in the range of60.7%-75%was achieved compared with the circuit structure which have no coarse-tuning current source.When the output frequency is138MHz, the output jitter is621.4ps.The entire circuit can achieve the desired design specifications.