Design Of Constrained Random Instruction Generating Platform Based On RISC-V Processor

With the process of integrated circuits becoming more advanced and the design scale becoming more and more complex,functional verification has become a huge bottleneck in the design of digital chips.As one of the most complex chips,microprocessors need a more efficient method of functional verification.As a fast and efficient verification method,random verification is an indispensable and efficient verification method in processor core-level verification.The characteristics of random validation are as follows: on the one hand,it can generate a large number of random test vectors quickly to reduce time and manpower costs;on the other hand,random incentives are generated randomly,and the combination of incentives is more diverse,which will produce many unexpected results,and may cover some defects that engineers can not anticipate.As an open source instruction set,RISC-V instruction set is free,compact,flexible and customizable,which makes it a new direction of microprocessor development at home and abroad.The purpose of this paper is to design an independent RISC-V constrained random instruction generation platform for random verification of RISC-V instruction set-based processors,so that it can be applied to functional verification of RISC-V instruction set-based processors from embedded applications to high performance computing.As a general platform,it can improve reusability.Starting from the requirement of actual project verification,this paper studies the strategy of random instruction generation at home and abroad,analyses its main functions and characteristics,and determines the strategy and method of instruction generation used in this paper,as well as the basic structure of the platform.A configurable method for generating constrained random instructions is proposed,and the system Verilog verification language is used to design it,which improves the reusability of the platform as much as possible.Before the design,the characteristics of RISC-V instruction set are carefully studied.According to the instruction structure and function,the instruction set is reasonably classified,and a large number of compilation tests are carried out.The Guidelines for Classification and Construction of Instruction Templates are compiled to ensure that the generated instructions strictly follow the RISC-V instruction format.The function characteristics,pipeline structure of the target processor are studied and analyzed.The scheme of generating excitation is formulated,including basic random instructions and constrained random instructions sequence of function points to be tested.Aiming at short time-consuming and high coverage,the structure of the whole platform is completed,various instruction templates are designed,random instruction libraries are formed,and some special instruction sequence generation structures are created.Configuration module is added to make the weight information and various constraints generated by instructions flexibly configure according to the change of coverage,so as to achieve more efficient instruction generation.In this paper,we take the open source processors optimized and improved by the project team as the research object,and use the platform to verify the functions of the processors.In the actual verification process,we optimized the platform,and added complex branch structure and exception handling structure.Finally,through running the platform,a large number of random test incentives are generated,and more than 90% of the verification tasks are completed.By analyzing and comparing the validation results with the original scheme,the platform has greatly improved the validation efficiency,and most of the functional points that are difficult to cover have been well covered in the process of platform improvement and optimization.As the core component of the verification system,it can be applied in more projects in an independent form,which greatly improves reusability.