Reasearch On Functional Verification Method Of IP Cores And Embedded Processors For SoC

With serious contradiction between rapid increasing SoC design complexity and demands of shorter time to market, functional verification has been a severe challenging problem of VLSI design. The research object of this thesis is about functional verification of IP cores and embedded processors. Verification platforms, verification tools, simulation flows, and verification methodologys are studied, and new techniques were proposed systematically to achieve high efficiency of IP design & verification and embedded processor functional verification. It notably improved the key basic components verification efficiency of SoC, and promoted SoC design and verification process. The contents and original contributions of this thesis are as follows:1.Virtual SoC platform based IP cores design and verification method. Under the direction of orthogonalization theory about computing and communication, we decomposed function space of IP cores into internal logics and communication interfaces, and designed general bus interfaces for IP cores to improve interface reusability. According to SPIRIT standard, IP description libraries were established which contained design and verification resources, and automatic IP integration flow was proposed for objective SoC systems. Through high level abstraction modeling method, we designed virtual SoC platform including systematic function models and peripheral device behavior models, providing one uniform verification environment for different IPs. Based on it, the stimulus spaces of IPs were decomposed orthogonaly, and the stimulus generation flows of IP communictioan interfaces and internal logics were optimized respectively. This method compressed stimulus redundancy and improved the efficiency and reusability of stimulus generation.2. Cycle accurated embedded processor model design method and system call translation method. Adopting OOP method, we decomposed processor models into two parts including pipeline architecture and functional modules and designed them respectively. Based on stable pipeline architecture, discrete functional modules were reconstructed to improve the exploring ablilty of processor models for processor design space. To support system call requests by the objective simulation program, we proposed direct channel translation method. Using register file module and bus interface unit of processor models, we extracted and translated parameters and data of system calls, implementing transmitting and translation between processor models and host systems. This method supported fast simulation process and well efficient debugging of objective simulation program.3. Verification platform and dynamic simulation flow of embedded processors. One integral verification platform for embedded processors was established, including test case part, random stimulus generator and resource library part, signal level verification sub-platform part, reference simulation model and result checking part, and coverage statistic part. Based on this platform, we proposed dynamic simulation flow method, which separated the simulation control flow with the verification platform scheduling flow. According to the method, verification scheduling center was established to design one-way main control flow for platform, and simulation flow control center was established to implement dynamic circular simulation flow. With one static compiling of verification platform, this method could implement dynamic stimulus generation and circular simulation process. It could notably compress compiling time consuming and improve simulation efficiency.4. Layered constrainted random stimulus generation method. For processor functional verification space, layered modeling method was proposed which designed layered functional verification resource library according to different abstraction granularities of instruction combinations. This library included scenario configuration layer and function operation layer, providing verification resources for random stimulus generation. Base on it, layer constrainted random stimulus generation method was proposed, in which constraints were injected into random stimulus generator layer by layer and passed down one way in chain between layers. It generated stimulus stream with high efficiency. This technique improved the quality and efficiency of random stimulus generation and enhanced the controllability and extendability of random process.All the methods and techniques proposed in this thesis had positive effects on improving the functional verification efficiency and quality of IP cores and embedded processors, and they could promote SoC design and verification process significantly.