Research On 32-bit RISC Microprocessor Design

Technology advances are providing overwhelming capability to integrate the whole electronic system into a single chip or a chip-set. The SOC (system-on-a-chip) paradigm reduces system power, size and cost as well as improves system performance. The key to the success of SoC design is the RISC microprocessor inside. And with the boost of semiconductor technology and the development of architecture technology, new applications need more and more high performance embedded microprocessors.This paper discusses the design methodology of a 32-bit high performance RISC microprocessor after various commercial mainstream RISC machines are introduced. It includes the following aspects: design of Instruction Set Architecture; design and implementation of RISC CPU﹑hierarchy memory system and other functional units with the emphasis is logic design. Functional verification that consists of system-level simulation and FPGA hardware prototyping is preceded and the results show goal is achieved and the performance characters such as speed and area of the design is good.This paper presents a new approach to partition the central controller unit and the architecture of the RISC CPU is determined based on the proposed approach. Compared to the traditional architecture, this architecture is easier to be debugged and extended. Moreover, the pipeline stall information doesn't traverse through multiple pipeline stages and it doesn't impact on the pipeline speed.This paper presents an approach to completely remove the bubbles in the pipeline caused by the RAW hazard.This paper presents an approach to shorten the program's execution time. Whether branch is taken can be judged and what is the next instruction to be fetched can be determined when the branch instruction is still in instruction decode stage. Thus, only a NULL operation is inserted after the branch instruction and the execution time of program can be significantly decreased.This paper also presents two principles to stall the pipeline and freeze signals corresponding to various pipeline stages are generated accordingly. The simulation waveform shows that the pipeline can be correctly stalled or unstalled by these signals.Different methods are adopted to generate the cache-inhibit flag according to whether it is sent to the instruction cache from the instruction MMU or it is sent to the data cache from the data MMU. The address space corresponding to instruction memory is always indicated cacheable, which is correct in function. The number of instruction memory access times is decreased and an asynchronous loop is removed to improve the timing of the whole system.Low power design technology in microprocessor is researched and a design methodology that supports dynamic and static power management is proposed.WISHBONE SoC interface is researched and the design methodology of a bus interface unit that is completely compatible with the WISHONE bus protocol is provided.This paper presents two approaches used in system-level simulation to manage configurations. Through these two approaches, the user of the simulation environment can determine which models are necessary in a special simulation with the least time and thus, the simulation efficiency is improved.The scheme of FPGA hardware implementation has been given at the end of this paper. The throughputs of software simulation and hardware emulation are compared and the essence of FPGA hardware prototyping is verified.In general, this RISC microprocessor based on design principle achieves high performance with low hardware cost. It has good scalability and open SoC interface and can be easily integrated into an electronic system.