The Functional Verification Of A High-performance DSP

With the increasing complexity and the increasing size of integrated circuits, especially for the processors with high complexity, functional verification has become a bottleneck in the design process. Successful functional verification can find errors in the design as early as possible, not only avoiding the financial and reputational loss caused by the designs errors, but also meeting the needs of shortening the design cycle, so that the product can get a larger share in the increasingly fierce competition in the market. Simulation-based verification and formal verification are the most commonly used methods for functional verification. For the simulation-based verification,how sufficiently the design can be verified,depends on the quality of the stimuli. The realization of most functions of a processor is relying on the execution of instructions. So to verify the correctness of a processor’s function, the key is generating high-quality instructions.The device under verification of this thesis is a digital signal processor, which is based on the very long instruction word architecture. The structure of the DSP is very complex. It can handle many different instructions, achieving a very powerful function. It was developed by a research institute of Chinese Academy of Sciences, and has successfully taped out. But the verification is not systematic and comprehensive. In order to guarantee that this DSP could run reliably and stably, a comprehensive verification of this DSP has been performed so that its functions were fully validated. The main contributions of this thesis are as follows.1. Based on the interpretation and analysis of the design specifications, the processor’s instruction templates are built up to guide the generation of assembly programs. A processor can only handle the instructions meeting the specific instruction syntax. According to the syntax of different instructions, functional constraints are written using the System Verilog language, and the instruction templates of all instructions are designed and realized. This is the foundation of the entire instruction generation platform for the automatic generation of legal instructions.2.The functional points of the design are extracted, the functional models are built, and the instructions are generated(using instruction templates) so that all the functional points are covered. During the process of instruction generation, coverage groups are designed to monitor which functional points have been covered by the generated instructions. Then, according to the report of functional coverage, the instruction generation platform is improved to, ensure comprehensive coverage of all the features. With the increase of confidence in verification, the verification cycle is also shortened due to coverage-guided instruction generation.3. An easy to operate constrained random instruction generation platform is built, which is automatic and scalable. To ensure the design can be verified comprehensively, a large quantity of stimuli is required. Based on the characteristics of the device under verification, this thesis has built a constrained random instruction generation platform which can generate instructions automatically. In addition, the platform provides rich interfaces to the users, while adding great scalability to support future expansions.