The Design Of Verification Reference Model And UVM Verification Of The Core With Reduced Instruction Set

With continuous breakthroughs in the semiconductor manufacturing process,the chip Si manufacturing process has broken through the 5nm size,and the complexity of chip design has increased sharply,posing new challenges to verification.RTL-based functional verification can quickly find design defects in the pre-silicon process of the chip and correct the design at the lowest cos t,which is the most effective way to ensure the quality of the chip design.The thesis studies a verification reference model for the core of a power fast charge management chip with RISC-V structure,which has important research value and practical significance for the research of RTL-based function verification.The thesis first analyzes the RISC-V architecture principles and project specifications,and designs a core reference verification model based on these.On the basis of the structural principle of the microprocessor and the reduced instruction set of the target core,using object-oriented programming methods,the verification reference model is designed as a UVM component derived from the UVM base class,uvm?component.It achieves the verification modeling of the instruction set and the parameterizable configuration design of the core's storage space,which enable the reference model to meet the requirements for complete verification of the instruction set and have good reusability.In order to finish the verification of the core,a modulelevel UVM verification platform is built,including core?ccb?monitor,core?scb,core?coverage and other UVM components,and the verification reference model is integrated into the UVM platform.By extracting the function points in the specification,the function test points are decomposed,and the constrained random stimulus is automatically generated by the script tool to realize the verification of the design under test(DUT).Besides,some direct testcases are planned to cover verification boundary space.In the later stage of the verification,a large number of regression tests are used to ensure the closure of all discovered design defects,and coverage is collected.Due to the integration of the verification reference model and the advantages of UVM itself,the built verification platform has excellent reusability and verification completeness.Finally,the analysis of simulation waveforms,code and functional coverage,etc.shows that the designed verification reference model well satisfies the need for random verification of the core instruction sequence,and completes the functional verification of the target.The functional coverage and the code coverage with the addition of exclude files reached 100%,and the verification results proved the correctness and effectiveness of the work in this thesis.