The Implementation Of Embedded Hardware Monitoring Of Data Error And Performance For LPDDR4

Recently,with the explosive development of the technology and information,smartphones and mobile devices have become popular,and the requirements for the performance of mobile devices are getting higher and higher.With the rapid development of So C in the direction of multi-function and high-performance,the system has higher and higher requirements for information storage.LPDDR4 SDRAM provides So C with low-power,high-capacity and high-bandwidth high-speed off-chip memory,providing efficient data transmission for mobile applications.At gigabit frequencies,any minor issue can cause data errors.In addition,the performance of the transmission will also affect the operation of the system.Therefore,a stringent request for the So C chip-level data stream and memory read or write control circuits has been put forward.With the increasing complexity of the chip itself,the iterative cycle of the chip is getting shorter and shorter.The pressure on the progress of the project,whether it is design or verification,is getting bigger and bigger.“No bug” is just a good ideal for the chip engineer.Actually,even if the verification is sufficient,there are still bugs exposed in the post-silicon test sometimes.The hidden dangers at this stage are difficult to debug.Many serious defects cannot find the root cause that will make the function verification cannot reproduce the defect problems,debugging encountered obstacles,delay the post-chip fix,which delay the time to market,furthermore will have a serious impact on the chip company.For baseband chips,data transmission is the most fundamental and important function,and the most problematic.In order to reduce the blindness of debugging when the system hung by DDR data error and DDR performance issue after the So C tape in,we develops this hardware debugging module – the embedded monitoring of data error and performance for So C postsilicon debug.The content of this paper is developed around the module of Intel's baseband chip,the Date Memory Interface(DMIF)module.This paper analyzes the upstream and downstream of the memory controller module and the So C data transmission path.It is divided into two parts for research: for LPDDR4 data error monitor,with the hardware implementation,CV(chip level verification)shall use special pattern to run the test which can reproduce the problem.After test done,software can read the register to know if LPDDR4 issue or not;For LPDDR4 performance monitor,with the hardware implementation,tester can get the LPDDR4 performance result with the register value after run the user case.It is useful for chip engineer to narrow down the issue to the specific block,such as CPU or No C or DDR.On the basis of completing the hardware monitor design of the LPDDR4 module,the Universal Verification Methodology(UVM)is used to build a verification platform.And then the author created the direct test cases and the random test cases with constrain to verify the function of the monitor.Completing the simulation and analysis,the code coverage and function coverage are up to 100%.The monitor can locate the problematic hardware block and reduce the post-silicon validation time and effort.Based on the current research work,this paper continues to explore and functionally improve the power consumption of this data transmission monitor.Considering some complicated scenarios in practical applications,analyzing the limitations of hardware monitors at this stage,and further proposing new ideas.The current hardware monitor of the LPDDR4 module has been integrated in the project of the author's internship and waiting for tape test.