| With the development and application of video technology,the demand for high-quality,high-resolution video is getting higher,but the previous generation of video compression standards,such as H.264,are difficult to meet people's needs.High-efficiency video coding is a new standard after H.264 formulated by ITU-T VCEG.HEVC inherits the H.264 coding framework and adds a number of new technologies.Under the same image quality,the size of the HEVC video stream is only half of H.264.However,with the introduction of new technologies,the complexity of the algorithm has increased dramatically,and the coding efficiency is difficult to meet application needs.As a special digital signal processing chip,the embedded DSP chip has strong advantages in digital signal processing.This paper focuses on the optimization of HEVC video coding based on TI's high-performance multi-core C66x-DSP to improve the real-time performance of the HEVC coding algorithm.The research work in this paper mainly includes four aspects: the construction of C66 xbased HEVC single-core coding system,optimization of HEVC algorithm,multi-core parallel implementation and DSP platform optimization technology application.(1)A multi-core application project based on the SYS / BIOS real-time operating system is built,and port the HEVC open source project homo-HEVC to the DSP platform.PC-side algorithm engineering has compatibility problems in the DSP development environment,so incompatible parts need to be adjusted or replaced.(2)This paper in-depth study the core technologies in HEVC,and improve the coding model of HEVC algorithm to reduce the algorithm complexity.In order to find the optimal encoding size,the HEVC encoder uses a large number of iterations and recursions to ensure the lowest cost after encoding.Although this way can get the best coding performance,it also sacrifice a lot of coding efficiency.A large number of studies have proved that there is a strong correlation between the temporal and spatial adjacent regions in the video,and leads to similar coding behaviors.Therefore,this kind of similarity can be used to improve the HEVC algorithm,reduce unnecessary iterations and recursions,and improve coding efficiency under the condition of minimal coding performance loss.(3)The multi-core parallel of the HEVC algorithm on the DSP platform is researched.TI's TMS320C6678 has eight CPU cores,one of which is used to manage the system and the other cores are used for parallel coding.In order to achieve parallelism,it is necessary to ensure that there is no dependency on the data processed by the DSP cores.In this respect,the HEVC algorithm framework has been modified to adapt parallel processing.(4)In order to further improve the coding efficiency,the HEVC algorithm is optimized through the optimization technologies under the DSP platform.System-level optimization can bring data closer to the CPU,accelerate data access;module-level optimization can improve the software pipeline of instruction execution,and execute more instructions in a single cycle.The HEVC video encoding system for the C66x-DSP platform in this paper has significantly improved in encoding efficiency through a variety of optimization technologies.The encoding efficiency is generally improved by dozens of times compared with the unoptimized system,realizing real-time encoding of SD video. |
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