Research And Optimization Of HEVC Decoder Parallel Processing

The development direction of video is high resolution, high frame rate and real-time, resulting in the existing video decoding algorithm has a high dependence on the hardware, to a certain extent hindered the development and promotion of the video industry. In this paper, a full study of the latest video codec HEVC technology, combined with multi-core microprocessor technology, research and optimize the parallel decoding HE VC technology,and the realization of three parallel decoding algorithm to reduce hardware dependency, while achieving superior decoding efficiency.In this paper, the HEVC serial decoder is realized on the basis of the deep study of the HEVC codec technology, and the architecture optimization, memory optimization, compiler optimization and SIMD instruction optimization of the decoder are carried out from the point of view of improving the parallelism of single instruction. Greatly improving the degree of single-processor instruction parallelism. Based on the serial decoder, a HEVC decoder based on pipeline parallel decoding algorithm is proposed and applied to TI TMS320C6678 multi-core board. Through the implementation and analysis of pipeline parallel decoding algorithm, grasp the advantages and disadvantages of parallel flow. In this paper, two new HEVC parallel decoding algorithms are proposed, which are data parallel decoding algorithm, data and function hybrid parallel decoding algorithm.Two hand algorithm integrates the encoding unit structure and syntax of HEVC, on the other hand, from the point of view of improving the utilization of hardware resources, a lot of iterative improvements have been made to the parallel algorithm frame flow, and finally the decoding performance is excellent and the processor occupancy rate High, easy to expand, easy to maintain HEVC parallel decoder.In this paper, the decoding rate of 1080p video can be up to 40fps and the CPU utilization is 81.3%, which is achieved by the research and optimization of the HEVC parallel decoding algorithm to improve the instruction parallelism and optimize the multi-thread parallel architecture.The performance of parallel decoding algorithm proposed in this paper is superior, and will promote the development of HD video industry in China.