| With the development of multimedia technology,people's demand for high definition video is gradually increasing.So high-definition video encoding and transmission technology have become the focus of research.A new generation of Video Coding Standard HEVC(High Efficiency Video Coding)is formulated On January 2013.At the same time,the development of embedded multi-core processor and high performance computer has provided the condition for the parallel processing system.In this paper,based on research and optimization of HEVC encoding and decoding algorithm on DSP,we design and implement a parallel decoding system based on TI TMS320C6678 as a multi core hardware platform.This dissertation makes a study on the key technologies of HEVC and the performance of multi core DSP.At first,rewrite the HM16.0 decoding software framework by C code.Secondly,optimize the decoding process architecture,and rewrite the code according to the characteristics of CCS compiler platform.The HEVC decoding system is transplanted into the single core of the hardware platform.Then analysis the complexity and time consuming of each module in the decoding process.The linear assembly optimization and entropy decoding algorithm optimization are adopted to improve the efficiency of the software.In order to achieve the HD real-time decoding system,it is needed to deploy the decoding system to a multi-core system..This dissertation design the multi-core parallel scheme based on the HEVC principle and the feature of C6678 platform.Then allocate the multi-core memory and set the flag of data transmission among the cores to control the process.The decoding system is transplanted into six cores of C6678 for entropy decoding,inverse transformation,interpolation,filtering and so on.At last,in order to reduce the time of data access and transmission,the principle of CACHE and EDMA is used to optimize the data flow.In this paper,the HD real-time decoding system based on the multi-core platform is realized. |
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