| H.265/HEVC,the new generation of video coding standard,which introduces many new features,these new features not only improve the coding efficiency,but also make the computing complexity of HEVC higher than the previous standard—H.264/AVC.In addition,HEVC standard aims at HD and UHD video applications,and these videos usually contain huge amount of data,these factors make real-time processing of HEVC standard video stream a big challenge faced by traditional single core processors.Fortunately,HEVC standard takes these problems into account when being developed,and providing many parallel tools,which can alleviate the real-time processing difficulties caused by high computational complexity and large amount of data.At the same time,the development of modern processors from single core architecture to multi-core architecture also facilitates the implementation of parallel processing algorithms.Therefore,the parallel processing algorithm of encoding and decoding of HEVC standard has become the subject of many researchers' attention.In this paper,the Tilera-GX36 multi-core processing platform has been used to study the parallel processing algorithm of HEVC decoding core module based on multi-core processing platform.The research content of this thesis mainly includes the following points:1.A combined parallel in-loop filtering algorithm based on multithreaded load balancing is proposed and implemented,which can realize the joint parallel processing of deblocking filter(DBF)and sample adaptive offset(SAO).Generally,because of the different texture of diverse regions in the image,the CTU is divided in various ways,which makes the number of boundaries to be filtered greatly different.When the CTU is used as the minimum parallel granularity for multi-threaded parallel,the load between different threads will be unbalanced.To solve this problem,a region division scheme has been proposed,which divides the image into several regions,and the number of boundaries to be filtered in each region is approximate.Then,a mapping table is used to distribute these areas to multiple threads for parallel processing,so as to achieve the load balance among the filtering threads.Finally,using cache technology,DBF and SAO are combined to reduce the delay between them and improve the overall parallelism of in-loop filtering.2.A parallel decoding algorithm of HEVC intra/inter frame fusion based on CTU is proposed and implemented.OWF algorithm is parallel decoding based on CTU-row,there will be the problem of thread idle due to the different computational complexity of CTU rows,which makes the decoding thread block in frame.The fine-grained wavefront parallel scheme based on CTU,can reduce the problem of intra frame decoding thread blocking when using CTU row as parallel granularity,but it does not consider the inter-frame CTU decoding parallel.In view of the problems existing in the two parallel decoding schemes,while the intra parallel granularity is refined,the inter CTU dependence can be further used to realize the parallel decoding of intra/inter frame fusion with CTU as the parallel granularity.If there is no CTU to be decoded in the current frame or there are idle threads,the idle threads can be directly used to decode the CTU satisfying the dependency in the adjacent frames.Thus,the thread idle is further reduced and the utilization rate of multi-core resources is improved.3.A parallel HEVC decoding algorithm based on core module fusion is proposed and implemented.If the proposed combined parallel in-loop filtering scheme and the parallel decoding algorithm of HEVC intra/inter frame fusion based on CTU are jointed directly with the frame level parallel entropy decoding scheme,the different parallel granularity and resource scheduling will bring overall delay to the system interior.To solve this problem,using pipeline parallel technology and hierarchical thread scheduling strategy to integrate the three modules,reduce the delay between modules and thread idle time,and improve the overall data throughput of the system.After that,the platform optimization of HEVC decoding is realized by using the characteristics of tilera multi-core platform.Experiments are carried out on the Tilera-GX36 multi-core processor,using libde265 as reference software.A variety of high-definition and ultra-high definition video streams have been tested,which were encoded without any parallel encoding tool.According to the experimental results,the parallel performance of the proposed parallel in-loop filtering scheme is about 9.1% on average higher than that of the previous fast fusion in-loop filtering algorithm;the average parallel performance of the parallel decoding algorithm of HEVC intra/inter frame fusion based on CTU is about 18.3% and 8.5% higher than that of the OWF and fine grained wavefront parallel scheme based on CTU;Compared with the fine-grained multi-level parallel decoding algorithm,the max parallel speedup of the HEVC parallel decoding algorithm based on core module fusion is increased by about 8.15% on average. |
