Study Of Low-Power Software Optimization Technology

Power Consumption has become a more and more important problem in current computer system, especially for processors. The major reasons are: 1) For embedded devices, they are powered by the battery. Constrained by the limited battery life time, power dissipation becomes another important system parameter besides performance and area. Compared with the speed of semiconductor technology development, the speed of the battery technology development is much lower. So it is significant for the futural battery-powered mobile devices to have better energy efficiency supplied with the limited energy consumption. 2) For high performance computer systems, in order to achieve higher performance, more and more transistors are integrated, which sharply increases the power dissipation. While rapid power increase further adds the chip packaging and cooling cost. In addition, the higher temperature increases the probability of the invalidation in integrated circuits (ICs) and leads to the decrease of the system reliability. For large-scale parallel systems, high power consumption consumes the huge energy resource. Although the progress of multi-core processors partly alleviates the conflict between the performance and power, multi-core processors will bring about the large heat and cooling problem. From the study for low power in recent years, multi-core based software low-power research has become the focus.A large number of novel low-power techniques at different levels including circuit, logic, architecture and software levels have been proposed to reduce power and energy. This thesis aims at study of low-power software optimization technology. Based on traditional performance-oriented optimization, we use dynamic voltage scheduling and shutting down technology to reduce power consumption while meeting the performance demand. In details, the major work consists of the following aspects: (1) Analyzing several low-power techniques and the power characteristics of on-chip memory; (2) Studying the enegy optimization method combining the processor with main memory. Two problems are considered: one is energy optimization with performance constraint and the other is energy-constrained performance optimization; (3) Studying low-power software prefetching optimization method, which combines static voltage scheduling with dynamic voltage scheduling; (4) Studying multi-core based energy optimization method for parallel programs. This method effectively applies shutting down technique and dynamic voltage scheduling on multi-core based energy optimization for parallel programs. The main contributions of this thesis are as follows:1. Proposing an energy-optimal energy optimization model based on processor and main memory, which remedies the deficiency that optimizes only the performance but the energy consumption. This model describes all kinds of situations appearing in the software prefetching. This model minimizes the energy consumption of the system by simultaneously adjusting processor's voltage and frequency and main memory's voltage and frequency.2. Proposing an energy-constrained energy model based on processor and mainmemory, which resolves the performance optimization under the limited energy supply. This model describes all kinds of situations appearing in the software prefetching. This model minimizes the execution time of the system within a limited energy constraint by simultaneously adjusting processor's voltage and frequency and main memory's voltage and frequency.3. Proposing static voltage scheduling based low-power software prefetching method.One side this method reduces the power dissipation by adjusting the voltage, and on the other side it achieves the further performance and power improvement by adjusting the prefetch distance. At last the average power dissipation of the whole program is no more than when no prefetch. That is, this method can improve the performance while eliminating the power increase due to software prefetching.4. Proposing dynamic voltage scheduling based low-power software prefetchingalgorithm PDP-DVS. This algorithm adjusts the processor's voltage level and guarantees the average power dissipation under the level when no prefetch by on-time monitoring the power of the system. Simulation results show that PDP-DVS can achieve the effective performance improvement without the power increase.5. Proposing the multi-core based energy optimization method for parallel programs.One hand this method uses shutting down technology to adjust the number of processors during the serial program execution, and on the other hand it uses dynamic voltage scheduling to adjust the voltage and frequency of each processor during the parallel program execution. Simulation results show this method can effectively reduce the energy consumption of parallel programs.