Design Of HEVC Video Decoder Based On TI C6678 Multi-Core Processor

With the development of modern science and technology, the video technology has become indispensable among people’s lives and works. With the growing demand of video experiences, the high-definition and ultra-high-definition video compression technology has become a trend in the field of video compression. High Efficient Video Coding (HEVC), the latest generation of video coding international standard, has been officially launched by the combination group of ITU-T VCEG and the ISO/EC MPEG video coding team in January 2013. Compared with the previous H.264, HEVC broughts about 50% decrease of bit rate for high-definition video compression. This shows that HEVC will definitely replace H.264 and become the common used video compression standard. This dissertation has designed the video decoding software based on TI C6678 multi-core processor to decode HEVC bitstream efficiently.(1) The key technologies of HEVC are introduced, and the software design is based on openHEVC software framework. The hardware platform of implementation is C6678, which is a TI multi-core DSP processor. C6678 has a strong fixed-floating-point processing capabilities, and it is very suitable for HEVC video decoding.(2) In the software design process, the debug of the decoding software is completed in the Visual Studio 2008 environment, and then it is transplanted into the single core of C6678, with code optimization performed. In order to improve the efficiency of HEVC decoding software, the linear assembly optimization on C66x processor is adopted, and the short functions which are frequently called in decoding modules were optimized to improve the decoding performance.(3) According to HEVC decoding framework, the software is divided into four parts: parsing module, reconstruction module, filter module, and storage module, the data communication between modules is achieved through the shared memory on the single core.(4) Each module of decoding software is transplanted into each corresponding core, and a primary core is used to ensure synchronization in the decoding process for task scheduling. Finally, by using EDMA of C6678, the video decoding data streams are optimized to further improve the decoding performance.