Power Optimization Of PCM Module At IC Front End

In terms of today's increasingly large and complex digital integrated circuit design,the industry's requirements for chip design have changed from simple pursuit of high performance and small area to comprehensive requirements for performance,area and power consumption.Not only does Low power consumption improve the stability of the system,but also ensures the normal operation of the circuit?What's more,low power can delay the service life of the chip,save the packaging cost and extend the standby life of mobile portable equipment,which can greatly improve the competitiveness of the chip.PCM(Pulse Coded Modulation)module is a system that is used for Bluetooth audio signal transmission between the RF(Radio Frequency)system and the AP(Application Processor)system.In order to reduce the power consumption of PCM module from the circuit design part of IC front-end,the following work is mainly done in this paper: The components of power consumption of integrated circuit and its influencing factors are analyzed comprehensively.Firstly,the paper analyzes the components of static power consumption in the circuit,the physical mechanism of leakage current and the formation reason of dynamic power consumption.Based on the basic functional requirements of the PCM module,the register-level code of the PCM module was designed with the hardware description language.The code quality was checked through nLint and the pre-simulation.The register-level code was integrated into the netlist,and the estimated power consumption result of PTPX was 7.325e-04 W.Secondly,the clock gating design is adopted in the circuit.The clock network in the register set is inserted into the clock control circuit to eliminate unnecessary clock activity and reduce redundant switching actions in the PCM circuit.After the addition of the clock gating structure,the total power consumption is 2.780e-04 W,saving 62.05% of the original power consumption.Thirdly,the sub-module asyn_fifo is designed with power gating method in order to reduce the unnecessary static power consumption in the sleep mode.The total power consumption optimization results of PCM is 2.262 e-04 W after the addition of the asyn_fifo power gating structure,saving 18.63% comparing to clock gating power result.The total power consumption of the two methods was saved by 69.12%.The low-power optimization method in this paper can greatly reduce the power consumption of PCM,which has a strong reference significance and practical value for the actual power consumption optimization of integrated circuits.