Design Of PLL Frequency Synthesizer Applied To Satellite Navigation Frequency Band

Frequency synthesizer is a high precision and high stability frequency generation system,which generates important local oscillation signals in satellite navigation receivers.Thanks to the rapid development of satellite communication,frequency synthesizer is used more and more widely.In today's satellite communication,the receiver is required to work in multi-mode band.Therefore,a wider frequency output range,lower system noise and power consumption,easily miniaturizing and integrating have become the design goals of frequency synthesizer chips.Considering the channel spacing and flexibility of channel switching,fractional-n frequency synthesizer has become a better choice to replace integern frequency synthesizer.In this paper,phase-locked loop is chosen as the structure of frequency synthesizer in satellite navigation receiver system.Based on the complexity of fractional frequency division PLL system,the top-down design flow is adopted in frequency synthesizer.Firstly,stability analysis and loop parameter determination of PLL are carried out by MATLAB,and then circuit level design is carried out by Cadence platform to ensure the reliability of PLL system.After completing the circuit level design of PLL system,it is necessary to evaluate the performance of the system and get the noise performance of the PLL system.When analyzing the noise performance of the system,the noise transfer function of the PLL system is deduced and analyzed firstly,and the noise model of the PLL system is established by the noise transfer function.The noise data obtained from the simulation of each module of the circuit are imported into the noise model of the MATLAB system,and the final system noise is fitted.Due to the influence of process corner and ambient temperature,the charge-discharge current of traditional operational amplifier charge pump will be worsened and mismatched.A new charge pump circuit is proposed in this paper,according to the different process corner and temperature of the working charge pump,different compensation currents are added to the charge pump circuit.Compensation current reduces the current mismatch ratio of the charge pump and optimizes the phase noise of the whole loop.In this paper,the characteristics of integer frequency division and decimal frequency division are analyzed in detail,and different decimal frequency division schemes are enumerated.According to the principle characteristics of digital modulator,a MASH1-1-1 digital modulator with input bit width of 20 bits is designed.The layout of MASH1-1-1 digital modulator is completed through the verification of Cadence platform.In this paper,a fractional frequency synthesizer is designed using SMIC 0.18 um CMOS process.The simulation results show that the output frequency range of frequency synthesis is from 1.45 GHz to 1.8 GHz,the phase noise is-121 dBc/Hz@1MHz,and the locking time is about 12 us.The PLL frequency synthesizer chip meets the requirements of the satellite navigation system receiver.