Design And Implementation Of A Sort Of Composition Navigation Computing Hardware Platform

With the structure and algorithm of SINS/GPS integrated navigation system becoming mature and perfect gradually,the embedded hardware platform adapting to the characteristics of SINS/GPS integrated navigation system has been put forward higher and higher requirements in practical application.Based on the requirement analysis of high-speed navigation operation and the characteristics of SINS/GPS integrated navigation system,this paper studies and designs an embedded navigation computing hardware platform based on DSP and FPGA to meet the requirements of micro-installation,high-speed operation,low power consumption and high reliability of hardware platform for navigation calculation.The core components of the design are TMS320C6748 DSP and EP4CE15F17 I FPGA,in which the DSP is responsible for navigation solution.With the rich internal resources and powerful programmable ability of the FPGA,the communication interface of the hardware platform can be extended to complete the receiving and caching of IMU and GPS signals.In hardware implementation,considering the harsh environment of electromagnetic interference of navigation computing hardware platform,the EMC design of peripheral circuit and memory circuit of hardware platform is made.The circuit layout and wiring are completed by Cadence 16.6 software,and the PCB chart of embedded navigation computing hardware platform is designed and drawn.Using the repeatable programming feature of the FPGA,six UART communication interfaces are extended in the chip,and the asynchronous serial transceiver IP core is designed by using Verilog HDL hardware programming language.The UART communication protocol and the timing of receiving and receiving are simulated to support the basic functions of RS-232 and RS-422 serial communication protocols and asynchronous serial transmission.In the design of the receiving module,16 times baud rate multiple interval sampling method is used to solve the problem of accurate alignment of the starting position and anti-noise interference in the receiving data process.In addition,the asynchronous FIFO designed in the platform is used to cache data,which solves the problem of data transmission across time domain,and designs an asynchronous FIFO empty-full state mechanism to control the asynchronous FIFO.In the realization of communication between DSP and FPGA,through comparative analysis of EMIFA interface access signal logic and UART control signal logic at the FPGA end,a suitable control logic decoding scheme is designed for serial expansion to ensure effective communication between DSP and FPGA.Finally,the function of the design is simulated by Modelsim-Alter software and the hardware platform is debugged.The results show that the designed navigation computing hardware platform can meet the requirements of SINS/GPS integrated navigation system for miniaturization,real-time,low power consumption and high reliability.