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Design Of Random Write/Read I~2C Serial Bus Interface Circuits Based On FPGA/HDL

Posted on:2009-07-16Degree:MasterType:Thesis
Country:ChinaCandidate:B LiuFull Text:PDF
GTID:2178360245963533Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
I~2C (Inter Integrated Circuits) is a serial bus used to connect chip components developed by Philips Company. With its stringent specifications, excellent performances, ease of use and many external devices with I~2C interface, it is widely used and welcomed.Digital ASIC design based on Field Programmable Gate Arrays (FPGA) is wildly applied with its high flexibility. In this paper, a random read/write I~2C interface circuits is discussed and implemented using Verilog/FPGA for data communication (read/write) with an E2PROM, achieving a 100KBps transmission rate. The design is simulated in Modelsim6.0 of Mentor Company, and downloaded in developing platform ISE9.1i of Xilinx. The external circuits are constructed for testing, and the implemented i2c interface circuit is tested with Logic Analyzer of Agilent via data acquisition. The testing results are analyzed, thus the designed result is verified.First of all, the development of microelectronics design and the design flow are illustrated, focusing on the HDL/FPGA design flow. Secondly, the I~2C serial bus were simply introduced, focusing on data transmission formats, and the timing sequences are listed of writing/reading AT24C02 E2PROM with I~2C interface. Thirdly, a random read/write I~2C interface circuits, testing module and inspecting display circuit are designed with Verilog_HDL. The interface circuit is realized with synchronous Limited State Machine (FSM). Testing module is designed to write data into the E2PROM at a designated address then read it out. Finally, the writed/read data are outputted to the external LED display circuits, thereby, the correctness of the design is verified directly by comparing the two displayed data. FPGA chips for download is Xilinx SPARTAN III XC3S200. Fourth, Agilent Logic Analyzer is used to acquire the transmission data, and the timing sequences are analyzed to verify the correctness of the circuits design.Finally, a summary is presented base on the research results, and prospects of the next stage are promoted.
Keywords/Search Tags:VLSI Design, Verilog _HDL, FPGA/CPLD, I~2C Interface
PDF Full Text Request
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