Optimized Design Of Low Density Parity Check Codes For NAND Flash Memory

NAND flash memory is a kind of non-volatile storage medium,which has the advantages of high storage density,low power consumption,and fast reading and writing.It is suitable for building large-capacity storage systems and is widely used in the Internet of Things,big data,cloud computing,mobile Internet,smart manufacturing and other fields.By scaling down NAND Flash to smaller cell size and using multi-level storage technology,the storage density of NAND flash memory is getting higher and higher,but the reliability and durability of flash memory are getting lower and lower.The bit error rate is getting higher and higher and traditional error correction codes are insufficient to meet the increasingly high error correction requirements of NAND flash memories.Low-density parity check codes(LDPC)are required to provide stronger error correction capabilities.The hardware implementation of the LDPC code is very complicated,and it will bring about additional read and write delays in the process of reading and writing data.Therefore,when studying the LDPC code applicable to the NAND flash memory,it is necessary to consider how to simplify the hardware implementation of the LDPC code and reduce its bringing reading and writing delays.In order to reduce the impact of LDPC codes on data reading and writing,a hardware scheme for LDPC codes with low resource consumption and low delay is proposed.The hardware scheme uses 5-bit fixed-point data for calculation,while using a look-up table method to simplify the addition process in the decoding process,thereby reducing resource consumption.In order to reduce the delay caused by the LDPC code,the run time is reduced by the parallel calculation of multiple units in the encoding and decoding process,while the time required for the decoding is reduced by streamlining the decoding iteration process.The test results on the hardware platform show that the LDPC code hardware program decreases the write speed by 0.24% and the read speed by 5.4%,which has little impact on data reading and writing.In order to further reduce the decoding delay of the LDPC code,an auxiliary decoding scheme based on decoding information in the same unit is proposed.The error rate of LSB page is lower than that of MSB page in the same unit.Take advantage of this feature,we can increase the decoding success rate,reduce decoding iterations and decoding delay when decoding MSB page,with the decoding information of same unit LSB pag,thereby reducing the decoding delay and improving read performance.Using the flash error model to test the auxiliary decoding scheme,the test results showed that the auxiliary decoding scheme increased the decoding success rate by up to 49% and reduced the number of decoding iterations by up to 40%.