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Research And Design Of High Speed And Low Power SAR ADC In 65nm

Posted on:2021-01-23Degree:MasterType:Thesis
Country:ChinaCandidate:X B TangFull Text:PDF
GTID:2428330614458575Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
With the development of digital integrated circuits,more and more analog integrated circuits are approaching the digital direction.ADC is still an indispensable part of the communication system as a bridge between an analog signal and a digital signal.Compared with other types of ADC,SAR ADC has the advantages of simple structure,small size and low power consumption,which is a hot topic in the industry and academia.In this thesis,A 10-bit 10 MSps SAR ADC is designed in 65 nm CMOS technology.In this thesis,the whole SAR ADC adopts a differential structure to increase the input range and reduce the noise.Compared with the traditional SAR ADC structure,it has the advantages of the large input range and anti-noise.The structure of the traditional gate bootstrap switch is analyzed,the linearity of the gate bootstrap switch is improved by using transmission gate structure instead of the MOS transistor.The structure of the comparator is analyzed,and the speed of the comparator is improved by reducing the shared node voltage.The capacitance DAC circuit is analyzed.In order to reduce the number of unit capacitances,the DAC capacitor array adopts a two-stage bridge capacitor structure and uses a split capacitor to separate large capacitance into small capacitance for independent control to obtain short establishment time.In this thesis,the circuit and layout are designed in 65 nm CMOS technology,the parasitic parameters are extracted and the performance of the circuit is simulated.At 10 MSps sampling rate,when the input signal is close to Nyquist frequency,the presimulation results show that the ENOB,SNDR and SFDR of the designed SAR ADC are achieved 9.84 bits,60.97 d B and 73.02 d B respectively,and the power consumption of the ADC is 35.64?W,an Fo M of 3.92 f J/conv.step.The post-simulation results show that the ENOB,SNDR and SFDR of the designed SAR ADC are achieved 8.70 bits,54.12 d B and 65.73 d B respectively,and the power consumption of the ADC is 104.27?W,an Fo M of 25.27 fJ/conv.step.
Keywords/Search Tags:SAR ADC, bridging capancitance, split capacitance, setting time, dynamic comparator, layout design
PDF Full Text Request
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