Design Of Low-voltage Fractional Divider For Navigation

Satellite navigation and positioning system is a radio system that can transmit high-precision,all-day navigation,positioning and guidance information,which has been widely used in military and civilian fields.Navigation RF chips are generally used for handheld devices,due to power supply constraints,low-power design has been a key indicator of the design of the navigation chip.As a key module in the navigation chip,the low-voltage low-power design of frequency synthesizer is particularly important.The main work of this thesis is to design a low-voltage fractional divider circuit for navigation transceiver.The whole system is based on 0.6 voltage power supply and 40 nm SMIC process.First of all,this thesis summarizes the current several major navigation and positioning systems and the current situation faced by China's self navigation system.And then summed up the navigation for the decimal divider design commonly used technology and circuit structure.In order to improve the working speed of the circuit and further reduce the power consumption,it is proposed that the traditional E-TSPC structure is added in the traditional E-TSPC structure for the design of the low voltage divider.Substrate control technology and critical path control technology,greatly improving the working speed of the circuit.For the implementation of the modulator,this thesis presents an improved maximum period sequence structure.With the error feedback controlling technology,the modulator achieves the maximum cycle length for all inputs,which greatly reduces the quantization error and improves the system noise.Finally,for the multi-mode programmable design,the E-TSPC-based prescaler PS counter structure,which using flip-flop structure,further reducing power consumption.The circuit design and layout design of the fractional divider are completed and the actual wafer test is carried out,which based on 40 nm SMIC process.The results show that the entire phase-locked loop system can work in the 0.6 voltage power supply,and the total power consumption of phase-locked loop is less than 1mA,in which fractional divider power consumption is less than 800?A,and frequency resolution is up to 25 Hz,and frequency division ratio covers 32~127,and the phase noise is less than-156.2dBc/Hz@1MHz and operating frequency is less than 4.5GHz which covers the working frequency band of all navigation system,the entry system meets the design requirements.