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Hardware Circuit Design Of IF Signal Playback Module

Posted on:2020-09-28Degree:MasterType:Thesis
Country:ChinaCandidate:J D HuoFull Text:PDF
GTID:2428330596476563Subject:Engineering
Abstract/Summary:PDF Full Text Request
The function of the signal playback module is to extract and process the data generated by acquisition or simulation,which is used in radar system or measurement system.The data acquisition system corresponds to the signal playback,and now the sampling rate and storage depth of the acquisition system can achieve very high indicators,forcing the signal playback system to have higher playback rate and longer sustainable playback time.As the sampling rate and storage depth of the acquisition system continue to increase,the signal playback system is moving toward to high playback rates,massive data storage,and long sustainable playback time.Due to the rapid development of highspeed DACs,the playback rate theory can achieve GHz level.However,because of the limited data capacity that can be cached by hardware modules and the limited data bandwidth of the industrial computer bus,it will inevitably lead to continuous time in playback of waveforms is very short.Therefore,in order to improve the signal playback time,the research on the sustainable playback of massive data has become a hot spot and a difficult point.The sustainable playback of signals requires a high-bandwidth communication bus.The PCI-Express protocol has attracted much attention due to its fast transmission speed and point-to-point transmission.In the past years,it has become a universal peripheral interface for computers.It is used in the field of connection between the network card and the graphics card.The high playback rate puts higher demands on the data interface of the DAC.The JESD204 B interface has a fast transmission speed and few data pins,and has gradually replaced the LVDS interface and is widely used in high-speed DACs.Based on the above situation,this paper studies the sustainable playback of highspeed signals and designs a massive data sustainable playback module on hardware circuit.The specific work content is as follows:1.Playback module circuit design.According to the requirements of the waveform playback system to pursue the complete details of the waveform signal,Author decides that the playback-system hardware platform is built based on the direct digital waveform synthesis(DDWS)technology.The data transmission bandwidth is calculated by the playback rate and resolution index,and the high-speed interface implementation scheme is compared,and finally the hardware design is realized by adopting the structure of “PCIe+FPGA+DAC”.Then,based on the main indicators,a demand analysis was conducted.This paper studies the reasons for the insufficient playback time of the traditional waveform playback board,and proposes a scheme for implementing data buffering with FPGA to realize sustainable playback of massive data.It is confirmed that the JESD204 B interface DAC is selected,the interface is briefly introduced,and the low jitter clock generation scheme is determined according to the clock requirements of the JESD204 B system.In the actual application,the specific design is completed to complete the hardware circuit design of the system.2.FPGA logic design.The FPGA logic is used to realize communication between the FPGA and the host computer,and the host computer sends waveform data and waveform playback commands to the FPGA through the PCIe bus.The AXI4 interface data of PCIe DMA is formatted by width and clock conversion,and then formatted to the DAC transmitter,and the JESD204 B transmitter code design and board-level chip logic configuration are completed at the same time.3.Testing and verification.A hardware test platform for testing the design were built.The main functions and indicators were tested in different ways,including the correctness of the massive data transmission,the continuity test and the final output analog signal quality test.Through the analysis of the test results,the rationality and feasibility of the sustainable-playback system scheme are verified.
Keywords/Search Tags:Data playback, JESD204B, Sustainable, Clock jitter
PDF Full Text Request
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