The Design Of A Radiation-hardened Gate Drive Circuit

Integrated circuits are widely used in many fields due to their advantages such as small size,low power consumption,low cost and high reliability.When the integrated circuit is used in the irradiation environment,it will inevitably suffer from various irradiation effects.Among them,the total dose effect is one of the important mechanisms affecting the performance of integrated circuits.It is of great significance to study the circuit with anti-total dose irradiation feature for the development of space industry.In this paper,the mechanism of the effect of total dose irradiation on MOS devices is described in detail.It is certified that the oxide layer in the MOS structure is the sensitive part of total dose irradiation.The total dose irradiation could cause performance degradation of the threshold voltage drift,off-state leakage current,and mobility decrease of the MOS device,which is essentially due to the accumulation of the trap charge in the oxide layer and the interface state of the Si/SiO₂ interface.In the gate drive,the principle of critical modules such as input interface circuit,dead-time circuit and high-side level shift circuit are analyzed,and then the whole circuit is built to perform functional simulation to confirm the implementation of various indicators.A new input interface module is proposed,based on an improved hysteresis comparator,which can discern standard CMOS or LSTTL,down to3.3V,and has amazing noise suppression capability while saving area cost.It is proposed to use the method of gate oxide fluorine implantation to carry out technology-level radiation hardened;the enclosed layout geometry is used for the low-voltage device radiation hardened.Using the device simulation method,the device was modeled by the Sentaurus TCAD software platform,and the process parameters of the device were determined through process alignment.The Insulator Fixed Charge model is used for simulating the effect of TID on MOS devices,the same conclusions as in the theoretical analysis were obtained.Modeling and simulating the availability of the enclosed layout geometry in this technology platform,and contrapose the difference between high-voltage LDMOS and ordinary low-voltage MOS,a new high-voltage LDMOS radiation-harden layout is proposed,which does not achieve good radiation resistance,but won't cause an increase in design area.The behavior of the post-irradiation circuit is simulated.It is found that the dead-time generation circuit is an radiation sensitive module.The reason of its radiation sensiblity is analyzed and a total dose hardened RC delay module is proposed.Then,the capability of radiation hardened of this module is verified by simulation.In this paper,the design of TID harden gate drive circuit is taken as the research topic.Based on the 1?m 600V BCD process platform,an TID radiation harden half-bridge gate drive circuit is designed.This chip can be compatible with input logic signals with a voltage of 3.3¹5V,and built-in dead-time circuit to prevent half-bridge branch straight through.The occurrence of the chip is reinforced with a layout-level TID radiation harden method,and it is expected that the total dose resistance of more than 100 krad?Si?can be achieved.