Research Of A Kind Of Total Ionizing Dose Radiation Hardened Basic Structure Of CMOS Circuits

With the rapid development of space technology and nuclear engineering technology,more and more CMOS integrated circuits are inevitably applied in the radiation environment and affected by various radiation effects.In order to ensure the reliability and performance of CMOS circuits,the research of radiation hardened technology has always faced severe challenges.The research topic of this paper is a kind of total ionizing dose radiation hardened basic structure of CMOS circuits.This paper presents a kind of total ionizing dose radiation hardened basic transistor structure,and mainly focus on the research of the total ionizing dose radiation tolerant capacity of the transistor structure and the influence of its structural characteristics on the total ionizing dose radiation tolerant capacity,and compares it with traditional layout hardened methods.In this paper,based on the basic principle of total ionizing dose effects,the physical process of total ionizing dose irradiation and the influence of total ionizing dose effects on the electrical characteristics of MOS devices are well studied.The total ionizing dose radiation hardened methods are introduced from the perspective of process and layout.Based on the concept of radiation hardened by design,this paper presents a kind of total ionizing dose radiation hardened basic transistor structure that achieves the radiation tolerant capacity by forming P+ doped regions on both sides of the source and drain regions of a conventional NMOS transistor.Then,this paper uses the Sentaurus TCAD software to simulate and compare the proposed transistor structure with the conventional NMOS transistor to verify its effectiveness on total ionizing dose radiation hardening.On this basis,a deformation structure is proposed to enrich its application range.And then,with the irradiation dose change,the corresponding performance degradation trend of the proposed transistor structure and corresponding deformation structure and the conventional NMOS transistor are further studied.And the differences in their output currents are studied as well.In view of the proposed transistor structure,this paper continues to study the influence of its structural characteristics on the total ionizing dose radiation tolerant capacity of the transistor.Firstly,this paper compares the difference of the radiation tolerant capacity of the transistor in the case whether the P+ doped regions are directly connected to the zero potential or not.The result suggests that the routing resources of the transistor layout can be saved by using the P+ doped regions without connection.Then,the influence of the concentration,width and junction depth of P+ doped regions on radiation tolerant capacity of the transistor are well studied by changing the structural parameters of the proposed transistor.And then the influence of the distance between the P+ doped regions and the N+ source/drain region on the breakdown voltage and the radiation tolerant capacity of the transistor are investigated.Based on the proposed transistor structure and the corresponding deformation structure is the scope of layout hardened method of total ionizing dose radiation,this paper further compare it with traditional layout hardened methods.First,this paper simulates and compares them on the total ionizing dose radiation tolerant capacity.And then,from the perspective of standard cell layout realization of basic gate circuits,this paper compares their area consumption.Based on the above comparison,it is possible to intuitively measure the application value of the proposed transistor structure and the corresponding deformation structure in engineering applications.