Radiation Hardened Digital Integrated Circuit IO Library Design

Aerospace Integrated Circuits will be affected by the radiation effects in the space environment. So, when we design the radiation hardened integrated circuits, it must ensure the performance in terms of functionality, performance and integration, especially in the radiation-hardened. The semi-custom design approach, which is based on the verificated cell library, can simplify the design process and shorten the design cycle, which can ensure reliability requirements of radiation hardened IC at utmost. Input/output circuit, as the important part of Integrated Circuits, can not only supply the output drive and receive the input signal, but also provide the ESD protection for the core circuits and I/O circuits itself.SMIC 0.13um process is adopted in this paper.A set of input and output radiation hardened cell library is designed. It includes the input unit, the output unit, the power supply unit, the ground unit and the filling unit, etc.Four inverters’chain is adopted in the input unit, which provides the input signals for the core circuits.It can shift the voltage level between the peripheral voltage (3.3V) and the core voltage (1.2 V) with the clamping effect of low supply voltage. In order to avoid introducing the indefinite state into the circuits, it needs take the week pullup input unit and the week pulldown unit. They are the same as the input unit, but the only different point is the pullup and pulldown which is achieved by adding a MOS in the input of the inverter. In order to make sure that the signal into the core circuit is clear, an Schmidt trigger is added in the inverters’chain. The noise in the input signal is filtered out by the different device threshold voltage. The primary and secondary protection consisting of GCNMOS and GGNMOS is adopted in the input units as the ESD protection circuits.The theory that the delay time between the NAND and the NOR is different, is adopted in the output unit to drive the pullup and pulldown of the inverter. It costs little compared with driving the device directly by the inverters ’chain. The six transistors’ structure and the GGNMOS is used as the level shifter and the ESD protection.The power supply and ground units include three units. One is used as the 1.2V for the I/O circuits. One is used as the 3.3V for the I/O circuits. One is used as the 0V for the I/O circuits, namely the ground voltage. One signal is added in the 3.3V units, which can make sure that it can supply a steady 3.3V. The filling units can make sure the I/O circuits into a standard splice and are used as the auxiliary power supply unit of the I/O circuits.Moreover, the radiation hardened design of I/O circuits is achieved through the layout. Its major effects are TID and SEE. TID will arose the change of the threshold voltage and leakage current. However, as the CMOS integrated circuit technology is scaled down, gate oxide thickness is getting thinner and thinner, threshold voltage drift in the 0.13um technology already can be ignored. Protection of leakage current is though the ring gate transistors. What affects the IO unit in SEE most is SEL, which is protected through dual ring.