Design Of CMOS Low Dropout Voltage Linear Regulator With High Performance

With the fast growing demand of portable electronic-products, pursuing high performance and low cost power management integrated circuit is still a hot field, so it is of great importance and has reality contribution to research the LDO linear regulator circuit.The object of this paper is to design low dropout voltage regulator (LDO) with TSMS 0.6μm CMOS technology. The LDO is used for Digital I/O power supply. It has achieved a wide input voltage which the range is from 3V to 5.5V and a stable output which is 2.8V, the largest load current is 100mA, the Dropout voltage is less then 100mV, the quiescent current is 25μA, the line regulation is 0.36%, the load regulation is 1.1%, the PSRR is larger then 70dB. The low power dissipation is realized. Additionally this LDO has the over-current and over-temperature protection circuits.In this paper, according to the simulation design specification, the specific circuit implications and designs of the major blocks of the LDO are discussed i.e., the reference circuit, the error amplifier, the pass device, the feedback resistor, the protection circuits, etc. The paper is focused the analysis on the frequency stability issue of the LDO and the power supply rejection ratio characteristics of the bandage References. The entire circuit simulation by the Cadence Spectre tool, the layout design and layout verification, backend simulation have been done by Virtuoso, Calibre and Spectre tools. The results of simulation meet the function requirement.