Design Of Fractional-N PLL Using Phase Interpolation Method

As a key component of wireless communication systems,phase-locked loops have been widely used.The traditional integer-N phase-locked loop cannot meet the high-precision system requirements due to its low frequency resolution.The fractional-N phase-locked loop can increase the frequency resolution without reducing the reference frequency and achieve high-precision frequency output.The fractional-N frequency-locked loop designed in this thesis consists of two parts: digital and analog part.The work contents and innovations are as follows:1)A hybrid phase/current-mode phase interpolator is presented to improve phase noise performance of ring oscillator based fractional-N PLLs.The hybrid phase/current-mode phase interpolator alleviates the bandwidth trade-off between VCO phase noise suppression and ?-?quantization noise suppression.By combining the phase detection and interpolation functions into XOR phase detector/interpolator block,accurate quantization error cancellation is achieved without using calibration.2)A self-biased ring voltage controlled oscillator uses a symmetrical load cell structure to help increase the output swing and suppress phase noise.The self-biasing circuit is used to provide a bias voltage to the ring oscillator,which improves the suppression of the oscillator power supply noise.3)In terms of stability,the sigma-delta modulator uses a three-stage MASH structure.The output of the sigma-delta modulator provides a perturbation to the input signal of the phase accumulator,so that its output does not exhibit a certain regularity,reducing the effects of fractional spurs.The phase-locked loop is designed in a 65 nm CMOS process.Under the operating conditions of 0.1~1.2V,the frequency range of the voltage controlled oscillator output is 0.125~1.148 GHz.When the bias current takes the minimum value,the phase noise of the voltage controlled oscillator is-102.087~-105.785dBc/Hz@1MHz;when the bias current takes the maximum value,the phase noise of the voltage controlled oscillator is-92.27~-92.94 dBc/Hz@1MHz.The resulting output frequency is 0.594~1.119 GHz.The lock time of the entire loop is less than 6 ?s and the RMS jitter is 4.96 ps.