Font Size: a A A

Research On NVM Based Main Memory Key Technology

Posted on:2018-06-27Degree:DoctorType:Dissertation
Country:ChinaCandidate:H B ZhangFull Text:PDF
GTID:1368330596452843Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
Accompanying the development of cloud computing and big data technology,the gap between computing throughput and bandwidth of memory hierarchies continues to increase.It becomes increasingly prominent to mitigate the Memory Wall and Energy Wall.Recently,the emerging Non-volatile memory(NVM)technologies are becoming research hot spots because of their high density,low energy and non-volatility.The coming of NVMs technology brings the revolutionary change of traditional memory hierarchy.However,the emerging memory technology also brings new questions such as performance optimization,limited lifetime and data security because of their asymmetric read/write latency,limited durability and non-volatility.These questions should be solved before NVMs being used into real applications.The NVMs can be used in almost each level of memory hierarchy including cache,memory and storage.Among them,the NVM based main memory is one of the important research aspects.This dissertation does researches on several key techniques of NVM based main memory,including data security,performance optimization on structure,main memory architecture and data placement of hybrid main memory. This dissertation propose an efficient shift based encryption mechanism Pin Tumbler Lock(PTL),which protects the data in racetrack memory from being attacked.PTL can protect all the data in racetrack main memory by completing encryption and decryption through shifting racetracks in nanoseconds.The security strength of encryption mechanism can be setup according to the application requirement.Compared to traditional methods,PTL can implement the same security strength with lower performance cost.Analysis demonstrate that PTL-128 achieves the same security strength of AES-128.Experimental results demonstrate that PTL get the same strength with Rand Pad with 7.3% less performance overhead and 4.1% less energy overhead. This dissertation propose a hybrid macro unit(HMU)based optimization mechanism of racetrack memory.This dissertation explore the design flexibility of memory design space and analyze the relationship between parameters and features in both device level and system level.Based on the designs flexibility,this dissertation propose a hybrid MU structure to make further optimization for read intensive applications.Experimental results shows that hybrid MU can outperform traditional MU 3% in performance and saving energy cost by 5% in average. This dissertation propose an optimization of shift insensitive racetrack main memory(SIRM).SIRM compose main memory using specific designed RM array and optimize the performance using two mechanism.Firstly,by designing subarray in main memory bank,SIRM implements the parallelism in the level of subarray.Secondly,SIRM decreases the collision of rowbuffer by shift insensitive data mapping method.Experiments demonstrate that SIRM can at most outperform traditional SSAM with 5.4% performance improvement with less energy cost. This dissertation propose an OS-level data distribution(OSDD)method in DRAMPCM hybrid main memory.In OSDD,data sections with respective read/write features in virtual address space were assigned to different memory medium by memory management module of operating system.In addition,OSDD needs no program label in application layer,thus making it transparent to programmer.The experiment showed that OSDD can get better overall performance than other methods.
Keywords/Search Tags:Non-Volatile Memory, Memory Architecture, Hybrid Memory, Phase Change Memory, Racetrack Memory
PDF Full Text Request
Related items