Research And Implementation Of Decoding Algorithm For Low Complexity LDPC Codes

Channel coding technology is an indispensable part of modern communication systems,which can provide reliable data transmission for communication systems.On the one hand,the LDPC codes have excellent error performance.On the other hand,the sparsity of check matrix makes it a low-complexity implementation.It is precisely because of these two advantages that LDPC codes stand out from the many error correction codes.This paper studied the low complexity decoding algorithm and implementation of LDPC codes.First,the theoretical knowledge of LDPC codes and related decoding algorithms were studied.The structural characteristics of the LDPC codes were described from three aspects.Then the good structure of the quasi-cyclic LDPC codes was introduced,and on this basis,the LDPC code recommended by CCSDS was derived.In this paper,several hard decision algorithms and soft decision algorithms were described,and their implementation complexity and decoding performance were analyzed and compared.Secondly,this paper analyzed two message passing strategies in the soft decision decoding algorithm: flooding message passing strategy and layered message passing strategy.Based on the fast convergence of layered message passing strategy,this paper focused on the principle of layered mini-sum decoding algorithm,and elaborated the low complexity of the algorithm.In order to improve the throughput of the layered mini-sum algorithm,a parallel layered decoding structure was introduced.By correcting the check matrix,messages can be transmitted between different layers while parallel decoding.This paper analyzed the error performance and complexity of various decoding algorithms through MATLAB simulation,and determined the number of quantization bits in hardware implementation.It can be seen from the simulation results that the convergence speed of the layered min-sum algorithm are close to the min-sum algorithm in twice,the performance of parallel layered mini-sum algorithm are close to the performance of layered min-sum algorithm.Finally,an LDPC code decoder based on parallel layered decoding structure was implemented on the FPGA.The structure of the check matrix determines that the number of layers of the decoder is 12.After introducing the overall decoding implementation,the design of each sub-module is elaborated,and the simulation results of each part on the FPGA are given.Finally,an LDPC code decoder with a clock rate of 200 MHz and a throughput of 46 Mbps is implemented on the hardware.