Shannon-limit-approaching Channel Codes And Implement On FPGA

Since Shannon theorem is proposed,to find the channel code whose performance can approach even reachShannon limit has been new focuse on field of communication.Polarcode is channel code to be found whose performance is closest to Shannon limit,and it is proposed by Arikan.Superiority of polar code can theoretically obtain strict proof,but there are some problems in practical applications and further research to need.And now LDPC code is widely used code, which is achannel code presented by Dr. Gallarger in 1962,however, due to the actual conditions, until the 1990 s it was only extensively researched and applicated.BecauseLDPC code has very good performanceand achieve a simple and efficient encoding way, so it has been widely appreciated and researched and has became strong competitor of the fourth generation mobile communications, satellite communications,andnetwork data transmission.QC-LDPC code is a subclass of LDPC codes, asquasi-cycle characteristics, so its encoding and decoding can be efficiently achievedon hardware.This paper first researches the process of Channel Combing and Channel Splitting,then analysises the polarization process based on these, and a schematic diagram of the channel polarization is given, as well as performance curves obtained by simulation under Gaussian channel. You can see that the code is based on the channel polarization to process information and have superior performance.Secondly, the paper givesa brief introduction of LDPC code encoding processand the encoding process for QC-LDPC code based on block quasi-cyclic structure. Thenthe process of randomly constructed QC-LDPC codes is further researched,details of the elimination of grith 4 and grith 6 is gived.The paper gives their comparative performance and constructs acode word in hardware implementation.Then the paper researches several soft-decision decoding algorithm for LDPC codesand carries out a detailed analysis of the performance,gives different software simulation results, and determines the correction factor. Finalizingthe layered decoding algorithm based on normalization algorithm is used in hardware implementations, and all data quantitative is set as 6 bits.Finally, analysis of the various structures of the LDPC code decoder determines the design of layered decoding architecture and implementation of each module, and then we use verilog hardware description language to complete the decoder design. Using Quartus software completes layout and integrated optimization of the decoder on EP3SL340H1152I4 of Alter and usingModelsim software completes decoder timing simulation. When the clock frequency is 50 MHz and the maximum iteration number is 5,the decoding throughput can reach 79.5Mbps.