Design And Implementation Of QC-LDPC Layered Decoder On FPGA

Since be rediscovered in1990s, because of great error correction capablilty which approachingShannon limit and advantage of low decoding complexity and high decoding throughput, LDPC codeshave attracted people’s attention and become new focuse on field of channel coding. Now LDPCcodes have being widely used in many mobile communication systems such as DVB-S2, CMMB andWi-Fi.With the development of research on LDPC codes, the implementation of LDPC codes onhardware also have high spead development. At the early stage, implementation architectures of mostdecoders for LDPC codes are serial architecture or parallel architecture. But these two architecturesall have serious disadvantages. After QC-LDPC codes being raised, semi-parallel architecture havebeing more and more used. Semi-parallel architecture archives a balance between decodingthroughput and hardware resources consumption.With further research, peoples proposed TDMP algorithm on the basic of TPMP algorithm.TDMP algorithm havs being implemented on hardware by the way of layered decoding architecture.This new architecture speed up decoding throughput by accelerating the convergence rate of decodingalgorithm and reduce resource consumption by reduceing the decoding complexity. Layered decodingarchitecture requires the weights of every columns in every layers of LDPC codes is not more than1,but many LDPC codes such as used in CMMB can’t reach this requirement. How to make layereddecoding architecture more widely adapt to different kinds of LDPC codes is the main question onthis paper.First, we introduce some basic knowledge of LDPC codes and propsd a new way for generatingparity-check matrix of QC-LDPC codes randomly which used for implementation of fast encoder.Secondly, we compare the error-correction performance of several kinds of soft-decisiondecoding algorithms. Finnally, Normalized Min-Sum algorithm is choosen for hardwareimplementation. Meanwhile, through software simulation, modified factor0.8is recommendedand quantitative is set as6bits.Thirdly, improve layered decoding architecture and make it can be used on non-layered LDPCcodes. Design a hardware architecture for3/4-rate,8192-length,(3,6) regular non-layered QC-LDPC.Finally, finished the hardware programe by using Verilog language, then fit and synthesized onthe Strtix Ⅳ familay FPGA devices by using Quartus Ⅱ. And Simulation result shows that the throughput can reach105.62Mbps at the clock frequency of100MHz.