Design Of A Fast Transient Response, High Efficiency, High Stability LDO Chip

Power management IC is an important component of the current electronic system. At present, power management circuit is developing towards the direction of high power density, high conversion efficiency, and high integration density. Low Dropout Regulator(LDO) has advantages including low noise, low-cost, simple application, and high reliability, which is always an important component of power management field. LDO has no output voltage ripple, complying with low noise occasions such as analog circuit and radio frequency circuit. This thesis studies LDO’s performance parameters, frequency stability, transient response, and its improvement methods, followed by a presentation of a fast transient response LDO designed by the author. Thereafter, a stimulation of the LDO chip is provided.This thesis begins with an introduction of LDO’s components and its operating theory. It also summarizes LDO’s each performance parameters and its meaning and computation expression. On this basis, the research discusses the effects of each component on LDO’s performance parameters, and then put forward the idea about how to make a comprise among each performance parameters during the LDO design. After that, the current thesis analyzes the distribution of polo-zero in common LDO, introducing traditional frequency compensation methods and the later developed new methods. Load transient response of LDO is discussed in detail, and influencing factors as well as methods of improving the transient response ability are provided.The author designed a fast load transient response LDO, which is based on the process of TSMC 0.5 μm CMOS. The thesis first gives a introduction of the LDO. the author compensates the voltage regulator’s loop, especially adopts a kind of buffer stage with high driving capability to improve the transient response speed of LDO. The result of simulation shows that the voltage drop is only 200 mV in the case of maximum load current being 500 mA. When the output capacitor is 10μF, and the load current jumps at full load within 1 μs, the over shoot of output voltage is within 21 mV, and the recovery time is 15 μs. the static current is 111 μA under the maximum load current, so the maximum current efficiency is 99.97%, meanings meets the design requirement.