DDR Memory Controller Validation And Measurement In High-definition Set-top-box Chip System

High definition digital set top box occupies a very important position in current digital communication and image processing technology.It is a terminal device for receiving digital signal and playing HD video program.With the development of communication technology and high-definition technology,set-top box products upgrade more and more quickly;the customers require a higher digital video quality,STB chip processing ability,bandwidth and data exchange capability.So it is very important to design a high-speed,stable DDR memory controller module.The latest DDR technology standard can realize the large capacity,high speed,and high bandwidth data processing ability,and improve the quality of the electronic products.This paper describes the trend of high-definition set top box and DDR storage technology development,analyzes the system structure of HD set-top box.Also,it focuse on the the hadware architecture,working principle and relevant technical specifications of the DDR memory.We design and compare the different planning of how to validation DDR3 memory controller.In the actual research,we adopt an optimal validate and test plan base on the DDR requirement,define the parameters of the memory controller in the SOC chip following the specification,and compare the result with the system expectation..At the same time through the measurement and analysis of signal waveform,it verifies existing design parameters,to meet the different voltage,temperature and other environmental requirements.Based on the current DDR memory technology,this paper proposes a general design and verification of the DDR memory controller in set-top-box chip.This design can effectively decrease the access latency,improve the data access bandwidth,and meet the stability in different system environment.It provides a certain value for the design and development in the future.