Research On Optimization Of Memory Access Scheduling Based On DDR3

In recent years,with the development of multicore microprocessor technology and integrated circuit technology,CPU performance has increased nearly 60% annually,while memory access latency has improved by only 7% per year.Memory access bandwidth and latency has become the key factor that restricts the further enhancement of computer performance.Memory controller is the bridge between the CPU and the memory,and how to effectively utilize the memory bandwidth becomes an important problem in the design of storage system.In this paper,we first analyze the DDR3 DRAM memory function,and then the characteristics of DRAM memory structure,DDR3 key technologies and working mechanism are discussed,and we summarizes the DDR3 read and write command timing specification,laying the foundation for the study of memory scheduling strategy.Then as for there are still lack of a standard evaluation for a universally accepted optimal scheduling scheme,an optimal scheduling model is established using the integer linear programming method based on DDR3 features and specifications.Through the analysis and solution of the model,it can efficiently complete the optimal scheduling of memory access requests.According to the optimal scheduling model,a modified ant colony optimization algorithm is proposed in this paper.Compared with the greedy scheduling algorithm and FCFS,the proposed algorithm can effectively reduce the delay and improve the bandwidth utilization,and provide a reference for the future improvement of hardware-based algorithms and the design of the next-generation DDR controllers.