Research On Coding Compression Method Based On SOC Test Data

With the continuous development and improvement of integrated circuit process technology,circuit integration has been increasing,and a system-on-a-chip(SOC)has been born.The number of intellectual property(IP)core multiplexed in the SOC is increasing,its functions and performance are continuously strengthened,and the production efficiency of the chip is improved,and the amount of test data used to detect circuit faults also increases,and correspondingly imposes new requirements on the capacity and bandwidth of the automatic test equipment(ATE)to store and transmit data,ultimately extending the SOC test time and increasing the test cost.Therefore,how to reduce the amount of test data has become a hot spot in the research of the integrated circuit industry.At present,one of the methods to solve the above problems is test data compression technology,which can effectively reduce the amount of test data,shorten the application time of the SOC test,and reduce the test cost.This dissertation takes coding compression as the main research content based on the research of fault model,fault simulation,test vector generation algorithm and various test data compression methods,proposed a new test data compression method based on dictionary coding.The main work are as follows:A data compression coding method for dictionary entries reuse is proposed.The test sets generated by Automatic Test Pattern Generation(ATPG)tools are divided into fixed-length data blocks,and the maximum compatible group is obtained by the cluster heuristic algorithm according to the data block compatibility,and the data blocks in these maximum compatible groups are divided into the first group,and the maximum compatible group is merged.After the data segment,the reference block is obtained and stored in the dictionary.By dividing the dictionary entry into sub-blocks,the number of reference segments is increased.The remaining unconsolidated data blocks are discriminated and grouped according to whether they can be partially reused by dictionary entries into a second group and a third group,and the data blocks of different groups are encoded according to the corresponding encoding rules.In this dissertation,the Atalanta test set is used to test the six largest sequential circuits in ISCAS-89 standard circuit.The experimental results show that the proposed coding algorithm improves the compression rate of test data and reduces the test application time.In addition,the decompression structure of the circuits is simple and easy to implement,and the hardware overhead is also within an acceptable range.