The Research Of SoC Test On Variable Length Coding

With rapid growth in integration and complexity of System-on-a-Chip (SoC), volume of test data required in large-scale integrated circuits test increases accordingly. However, the storage capacity, frequency and bandwidth of the traditional automatic test equipment (ATE) are limited, which results in some problems in SoC test, such as long test application time and cost of test. These can be solved by replacement of high-end ATE, but it will lead to an increase in cost of test.Test data compression technology can effectively reduce time and test of cost. In the strategy of variable-to-variable run-length coding, variable-length original data is encoded with variable-length codeword, which obtains an excellent compression performance.To solve problems in SoC testing, such as storage space and bandwidth of ATE, a test data compression scheme of part-coding based on variable-to-variable run-length coding is proposed in this dissertation. Analysis results indicate that the run of 0s, whose length is zero, appears frequently and even exceeds more than half in some Mintest test sets. If these runs are encoded in traditional coding schemes, the codeword length is longer than the original one. For improving compression rate, the runs of 0s with non-zero length are encoded only in part-coding scheme. When length of a 0s run-length is zero, the encoded word is "1", occupying single bit, and part-coding code table is used for encoding 0s runs with non-zero length. Experimental results show the method can improve compression rate.Subsequently, a novel scheme of group-expansion coding is proposed. Through analysis of test data, it is found that the test sets not only contain lots of runs of 0s, but also runs of 1s. The scheme of group-expansion coding, which expands twice capacity of every group, is also a kind variable-to-variable coding. It is more widely adapted to different encoding objects, because the method encodes any length of runs of 0s and 1s. Furthermore, the decoder of the method is independent of the circuit under test. Thus, it is especially suited for testing of the IP core which has no structural information. Theoretical analysis and experimental result show that it has a higher test data compression rate than some published schemes.