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The Research Of SoC Test Data Compression Method Based On Partial Reusing And Statistic Coding

Posted on:2012-12-06Degree:MasterType:Thesis
Country:ChinaCandidate:X E HuangFull Text:PDF
GTID:2178330335961618Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
In the manufacturing processes of Integrated Circuit (IC), the testing in circuit has become more and more important. With the higher integration of IC, the scale of circuit will be huge, and the function of circuit will be enhanced, testing has become more complex and the percentage of testing costs in overall costs will continue increasing. The use of IP core reuse technique in System-on-a-Chip (SoC) can reduce the development cycle of the chip and improve the production efficiency of the chip. However, it also brings many problems. For example, this technique brings about the improvement of SoC integration and the increasing of test data, which has brought a huge challenge in the memory capacity and bandwidth of Automatic Test Equipment (ATE).At present, the technique of test data compression is one of effective approaches to solve those problems. By analyzing a variety of efficient test data compression methods, this dissertation proposes two novel test data compression schemes based on partial data block reusing. The main works are as follows:(1) This dissertation firstly introduces the background knowledge of SoC and the basic principles of SoC testing. Then it analyzes the challenges of SoC testing, and focuses on the analysis and summary of several effective methods on test data compression.(2) This dissertation presents a novel test data compression method based on partial data block reusing. Firstly, this method confirms a reasonable range of the data block length by analyzing the data blocks'correlation and parts of the data blocks'reusability. Then, it assigns reasonable values to do-not-care bits so that blocks'correlation and reusability are better. At last, it finds an optimal reference data block from a lot of data blocks for each test vector. And it employs the data blocks'correlation and parts of the data blocks'reusability to achieve a better compression ratio.(3) This dissertation presents a test data compression method based on partial reusing and Optimal Selective Huffman Coding. Firstly, after dividing test data into fixed length data blocks,this method improves the data blocks'correlation and parts of the data blocks'reusability by the reasonable assignment to do-not-care bits. Meanwhile, it also increases the frequency of high-frequency data blocks, and improves the compression ratio. Secondly, based on the principle of reusing,low-frequency data blocks can be divided into two parts. One is reused block and the other is un-reused block. Then it counts the sum of the frequency about the two kinds of data blocks. Finally, high-frequency blocks, reused blocks and un-reused blocks participate in Huffman coding to improve the ratio of compression.For the ISCAS'89 benchmark circuit,the experimental results show that the two coding methods proposed in this dissertation can effectively compress the test data set and have general applicability.
Keywords/Search Tags:System-on-a-Chip, Relativity of data block, Compression/Decompression, Statistics, Data block reusing
PDF Full Text Request
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